Optical proximity correction (OPC) plays a vital role in the lithography process development of current semiconductor devices. OPC is utilized to achieve the ideal pattern shape because of the limitations of optical resolution. However, the lithography process design has become increasingly more complex due to the abundant use of OPC features. Hence, metrology requests for CD-SEM have also become more complex and diverse in order to characterize the critical OPC models.
The number of measurement points for OPC model evaluation has increased to several hundred points per layer, and metrology requests for realized pattern shapes on the wafer are no longer simple one-dimensional measurements. Metrology requests include not only the traditional line width measurements, but also edge placement error (EPE) and corner rounding to identify line end shortening.
Several researchers have proposed using the design layout as a template instead of the SEM image for the recipe creation of CD-SEM and EPE measurement. However, it is very difficult to achieve good matching results between the design layout and the SEM image in practical processing times.
Hitachi High-Technologies has developed a robust and quick matching engine between the design layout and SEM image bitmap. The new system, incorporating this new matching engine, can automatically create a practical recipe from the coordinate information of measurement point and the design layout information, such as GDSII. As a result, the new system can vastly reduce the amount of time and number of operations required to generate a several-hundred point CD-SEM recipe for OPC evaluation.
This study demonstrates the capability and presents evaluation results of this new matching engine. This new capability has proven to be a viable solution for OPC evaluation, and its efficiency will allow for quicker information turns between design and manufacturing.

A new matching engine between design layout and SEM image of semiconductor device

The increasing complexity and data volume of VLSI designs demand an efficient optical proximity correction (OPC) technique. In this paper, we address the issues related to the gate bridge, which is serious in sub-quarter micron technology, and the wide range of contact CD (Critical Dimension) variation. We present the efficient gate CD control method by introducing the critical area correction. In addition, the contact CD variation is reduced under the target CD range due to the combination of the contact biasing and the process calibration. The correction time and output data volume are drastically reduced by the hierarchical data manipulation using a DRC (Design Rule Check) tool, which basically exploits the characteristics of the design layers in ASICs. The newly proposed incremental on-line violation filtering method also reduces the correction cycle time significantly.

An efficient rule-based OPC approach using a DRC tool for 0.18 /spl mu/m ASIC

A method of developing a photoresist layer on a semiconductor wafer in a developing chamber includes applying a developer to the photoresist layer, applying an alcohol rinse to the photoresist layer, and drying the wafer

System and method for developing a photoresist layer with reduced pattern collapse

The minimum feature size of new generation memory devices is approaching down to 50 nm era. And a very precise CD control is demanded not only for cell layouts but also for core and peripheral layouts of DRAM devices. However, as NA of lens system grows higher and higher and Resolution Enhancement Techniques (RETs) becomes more and more aggressive, isolated-dense bias increases and process window for the core and peripheral layouts decreases dramatically. So, the burden of OPC increases in proportion and it is requisite to verify as many features as possible on wafer. If possible, it would be desirable to verify all the features in a die. Recently, a novel inspection tool has been developed which can verify all kinds of patterns on wafer based on Die to Database copmarison method. It can identify all the serious systematic defects of nm order size error from the original layout target and feed back the systematic error points to OPC for more accurate model tuning. In addition we can obtain the full field CD distribution diagram of some specific transistors with hundreds of thousands of measurement data. So, we can analyze the root cause of the CD distribution in a field, such as mask CDU or lens aberrations and so on. And we can also perform Process Window Qualification of all the features in a die. In this paper, OPC verification methodology using the new inspection tool will be introduced and the application to the analysis of full field CD distribution and Process Window Qualification will be presented in detail.

New OPC verification method using die-to-database inspection

As the design rule shrinks down, various techniques such as RET, DFM have been continuously developed and
applied to lithography field. And we have struggled not only to obtain sufficient process window with those
techniques but also to feedback hot spots to OPC process for yield improvement in mass production. OPC
verification procedure which iterates its processes from OPC to wafer verification until the CD targets are met and
hot spots are cleared is becoming more important to ensure robust and accurate patterning and tight hot spot
management.
Generally, wafer verification results which demonstrate how well OPC corrections are made need to be fed back to
OPC engineer in effective and accurate way. First of all, however, it is not possible to cover all transistors in full-chip
with some OPC monitoring points which have been used for wafer verification. Secondly, the hot spots which
are extracted by OPC simulator are not always reliable enough to represent defective information for full-chip.
Finally, it takes much TAT and labor to do this with CD SEM measurement. These difficulties on wafer verification
would be improved by design based analysis. The optimal OPC monitoring points are created by classifying all
transistors in full chip layout and Hotspot set is selected by pattern matching process using the NanoScope TM , which
is known as a fast design based analysis tool, with a very small amount of hotspots extracted by OPC simulator in
full chip layout. Then, each set is used for wafer verification using design based inspection tool, NGR2150 TM . In this
paper, new verification methodology based on design based analysis will be introduced as an alternative method for
effective control of OPC accuracy and hot spot management.

OPC verification and hotspot management for yield enhancement through layout analysis

As optical lithography has been pushed down to its theoretical resolution limit, the application of very high NA and aggressive Resolution Enhancement Techniques (RETs) are required in order to ensure necessary resolution and sufficient process window for DRAM cell layouts. The introduction of these technologies, however, leaves very small process window for core and peripheral layouts. In addition, new generation DRAM devices demand very precise CD control of the core and peripheral layouts. It implies that the time has come to keep a very watchful eye on the core and peripheral layouts as well as DRAM cells. Recently, Process Window Qualification (PWQ) technology has been introduced and is known to be very useful to estimate process window of core and peripheral layouts. Also, novel measurement system which can compare SEM image with CAD data is being developed and it can be of great help to evaluate OPC accuracy and feed back the CD deviation to OPC modeling. Last but not least, New Mask Qualification (NMQ) is proposed to verify very low K1 lithography by comparing with relatively high K1 lithography. In this paper, most effective OPC verification methodologies for sub-100nm node are discussed.

OPC accuracy and process window verification methodology for sub-100-nm node

We analyzed the local pattern collapse by KLA-2132 in patterning gate line of 0.18 micrometers on the Poly-Si/WSix/Si 3 N 4 , where the thickness variation of Si 3 N 4 (Nitride) film affected on the substrate reflectivity. By thickness split experiments of organic bottom anti- reflective layers (ARLs), we showed the effect of thickness variation of Nitride on the resist pattern collapse. We investigated the contribution of various factors to the pattern collapse. First of all, we focused on the CD variation due to substrate reflectivity variation to remove patterns of tolerable aspect ratio. In order to obtain better CD uniformity by tight reflectivity control considering the thickness variation of Nitride film, we optimized anti-reflective layer process using inorganic ARLs. As an inorganic ARL, we used PECVD SiOxNy:H(SiON) of which optical constants were changed by deposition conditions. We compared typical positive-tone DUV resists, of acetal based with environmentally stable chemically amplified photoresist type, to clarify the effect of resist and organic bottom ARL materials.

Analysis of resist pattern collapse and optimization of DUV process for patterning sub-0.20-μm gate line

Sensitivity of newly developed photo mask inspection tool with reflective optic was evaluated for 45nm DRAM device.
To get the required defect sensitivity of mask, printability of mask defect on wafer were simulated using in house
simulation tool. Simulation results were compared with inspection results. Characteristic and sensitivity comparison
between conventional transmissive and reflective optic tools were evaluated for several types of mask layer of 45nm and
55nm DRAM according to pixel size of detector of inspection tools. This reflective optic with short working distance
was equivalent in sensitivity to transmissive optic tool. Mask for 45nm DRAM can be qualified by current status of the
art inspection tools.

Mask inspection method for 45nm node device

As device pattern size is shrinking to below 65nm on wafer, the small amount of CD variation on wafer field determine the wafer yield. Most of the wafer field CD variations come from mask CD variations across mask field. By correction of dose and transmittance on mask using wafer field CD variation, wafer CD uniformity can be extremely enhanced. To get fine correction of wafer field CD uniformity, we have developed various methods to get close correlation of mask and wafer field CD uniformity by SEM, scatterometry and area CD methods. Especially, area CD from CD-SEM and optical CD measurement tools are developed to represent each area of masks. By optimizing measurement methods, repeatability and correlation of CD uniformity between masks and wafers are enhanced to get more than 0.7 of correlation between mask and wafer. And these give us the correction method to compensate field CD variation of maskCD on wafer. More than mask CD uniformity requirement on 65nm tech of DRAM memory device has been achieved.

The study for close correlation of mask and wafer to optimize wafer field CD uniformity

In this work, CD control issue at 0.37 K1 optical lithography will be discussed in terms of lens aberration sensitivity. Specific aberration terms that affect CD asymmetry on isolation, word line and storage node layers were investigated by simulation and CD uniformity measurement. The lens aberration was characterized by LITEL ISI (In-Situ Interferometer) and the aberration sensitivity was investigated by Solid-C aerial image simulation. From this result, we can understand the relation between some significant Zernike terms and CD control of DRAM’s critical layers.

Goomin Jeong

Papers

OPC accuracy and process window verification methodology for sub-100-nm node

Analysis of resist pattern collapse and optimization of DUV process for patterning sub-0.20-μm gate line

Mask inspection method for 45nm node device

The study for close correlation of mask and wafer to optimize wafer field CD uniformity

CD control at low K1 optical lithography in DRAM device