A pattern inspection apparatus is used for inspecting a fine pattern, such as a semiconductor integrated circuit (LSI), a liquid crystal panel, and a photomask (reticle) for the semiconductor or the liquid crystal panel, which are fabricated based on data for fabricating the fine pattern such as design data. The pattern inspection apparatus includes a reference pattern generation device configured to generate a reference pattern represented by one or more lines, comprising one of a line segment and a curve, from the data, an image generation device configured to generate the image of the pattern to-be-inspected, a detecting device configured to detect an edge of the image of the pattern to-be-inspected, and an inspection device configured to inspect the pattern to-be-inspected by comparing the edge of the image of the pattern to-be-inspected with the one or more lines of the reference pattern.

Pattern inspection apparatus and method

As minimum feature size and pitch spacing further decrease, triple patterning lithography (TPL) is a possible 193nm extension along the paradigm of double patterning lithography (DPL). However, there is very little study on TPL layout decomposition. In this paper, we show that TPL layout decomposition is a more difficult problem than that for DPL. We then propose a general integer linear programming formulation for TPL layout decomposition which can simultaneously minimize conflict and stitch numbers. Since ILP has very poor scalability, we propose three acceleration techniques without sacrificing solution quality: independent component computation, layout graph simplification, and bridge computation. For very dense layouts, even with these speedup techniques, ILP formulation may still be too slow. Therefore, we propose a novel vector programming formulation for TPL decomposition, and solve it through effective semidefinite programming (SDP) approximation. Experimental results show that the ILP with acceleration techniques can reduce 82% runtime compared to the baseline ILP. Using SDP based algorithm, the runtime can be further reduced by 42% with some tradeoff in the stitch number (reduced by 7%) and the conflict (9% more). However, for very dense layouts, SDP based algorithm can achieve 140× speed-up even compared with accelerated ILP.

/pdf/layout-decomposition-for-triple-patterning-lithography-1bak910stu.pdf

Layout decomposition for triple patterning lithography

A semiconductor device includes a substrate and a number of diffusion regions defined within the substrate. The diffusion regions are separated from each other by a non-active region of the substrate. The semiconductor device includes a number of linear gate electrode tracks defined to extend over the substrate in a single common direction. Each linear gate electrode track is defined by one or more linear gate electrode segments. Each linear gate electrode track that extends over both a diffusion region and a non-active region of the substrate is defined to minimize a separation distance between ends of adjacent linear gate electrode segments within the linear gate electrode track, while ensuring adequate electrical isolation between the adjacent linear gate electrode segments.

Dynamic array architecture

In double patterning lithography (DPL) layout decomposition for 45 nm and below process nodes, two features must be assigned opposite colors (corresponding to different exposures) if their spacing is less than the minimum coloring spacing [11, 9, 5]. However, there exist pattern configurations for which pattern features separated by less than the minimum color spacing cannot be assigned different colors. In such cases, DPL requires that a layout feature be split into two parts. We address this problem using a layout decomposition algorithm that includes graph construction, conflict cycle detection, and node splitting processes. We evaluate our technique on both real-world and artificially generated test cases in 45 nm technology. Experimental results show that our proposed layout decomposition method effectively decomposes given layouts to satisfy the key goals of minimized line-ends and maximized overlap margin. There are no design rule violations in the final decomposed layout.

http://www.cecs.uci.edu/~papers/iccad08/PDFs/Papers/06C.1.pdf

Layout decomposition for double patterning lithography

Double patterning lithography has been one of the candidates for sub-40nm patterning era, and has a lot of process
issues to be confirmed. Last year, we presented the issues in double patterning lithography with a real flash gate pattern.
Process flow was suggested and CD uniformity due to overlay was analyzed. And the layout decomposition and the two
types of double patterning of positive and negative tone were studied with 1-dimensional pattern. In this paper, the
implementation to DRAM patterns is examined, which consist of 2-dimensional patterns. Double patterning methods and
the selection of their tone for each layer are studied, and the difficulties from the randomness of core pattern are also
considered. As a result, DRAM patterns have more restrictions on the double patterning method and selection of tone,
and the aggressive layout decomposition should be designed to solve the difficulty in core patterning. Therefore, 37nm
DRAM layout can be patterned and the overlay control and cost still remain as dominant obstacles.

Issues and challenges of double patterning lithography in DRAM

Double patterning lithography is very fascinating way of lithography which is capable of pushing down the k1 limit below 0.25. By using double patterning lithography, we can delineate the pattern beyond resolution capability. Target pattern is decomposed into patterns within resolution capability and decomposed patterns are combined together through twice lithography and twice etch processes. Two ways, negative and positive, of doing double patterning process are contrived and studied experimentally. In this paper, various issues in double patterning lithography such as pattern decomposition, resist process on patterned topography, process window of 1/4 pitch patterning, and overlay dependent CD variation are studied on positive and negative tone double patterning respectively. Among various issues about double patterning, only the overlay controllability and productivity seemed to be dominated as visible obstacles so far.

Positive and negative tone double patterning lithography for 50nm flash memory

The minimum feature size of new generation memory devices is approaching down to 50 nm era. And a very precise CD control is demanded not only for cell layouts but also for core and peripheral layouts of DRAM devices. However, as NA of lens system grows higher and higher and Resolution Enhancement Techniques (RETs) becomes more and more aggressive, isolated-dense bias increases and process window for the core and peripheral layouts decreases dramatically. So, the burden of OPC increases in proportion and it is requisite to verify as many features as possible on wafer. If possible, it would be desirable to verify all the features in a die. Recently, a novel inspection tool has been developed which can verify all kinds of patterns on wafer based on Die to Database copmarison method. It can identify all the serious systematic defects of nm order size error from the original layout target and feed back the systematic error points to OPC for more accurate model tuning. In addition we can obtain the full field CD distribution diagram of some specific transistors with hundreds of thousands of measurement data. So, we can analyze the root cause of the CD distribution in a field, such as mask CDU or lens aberrations and so on. And we can also perform Process Window Qualification of all the features in a die. In this paper, OPC verification methodology using the new inspection tool will be introduced and the application to the analysis of full field CD distribution and Process Window Qualification will be presented in detail.

New OPC verification method using die-to-database inspection

New generation DRAM devices such as high speed Graphic DRAMs demand smaller size transistors and very precise CD control. However, the application of very high NA and aggressive Resolution Enhancement Techniques (RETs) increases Isolated-dense bias and leaves very small process window for isolated transistor patterns. It implies that a very aggressive and also very delicate OPC work is required for these new generation devices.
A novel measurement system which can compare CD SEM image with CAD data has been developed and we were able to systematically calibrate OPC modeling and verify modeling accuracy by connecting this measurement system with OPC tools. In this paper, the functions of the novel measurement system are presented and the application to the OPC calibration and OPC accuracy verification are presented. This novel measurement system was very useful for 2D model calibration. We were able to enhance OPC accuracy through this systematic OPC calibration and verification methodology.

OPC accuracy enhancement through systematic OPC calibration and verification methodology for Sub-100nm node

As optical lithography has been pushed down to its theoretical resolution limit, the application of very high NA and aggressive Resolution Enhancement Techniques (RETs) are required in order to ensure necessary resolution and sufficient process window for DRAM cell layouts. The introduction of these technologies, however, leaves very small process window for core and peripheral layouts. In addition, new generation DRAM devices demand very precise CD control of the core and peripheral layouts. It implies that the time has come to keep a very watchful eye on the core and peripheral layouts as well as DRAM cells. Recently, Process Window Qualification (PWQ) technology has been introduced and is known to be very useful to estimate process window of core and peripheral layouts. Also, novel measurement system which can compare SEM image with CAD data is being developed and it can be of great help to evaluate OPC accuracy and feed back the CD deviation to OPC modeling. Last but not least, New Mask Qualification (NMQ) is proposed to verify very low K1 lithography by comparing with relatively high K1 lithography. In this paper, most effective OPC verification methodologies for sub-100nm node are discussed.

Jaeseung Choi

Papers

Issues and challenges of double patterning lithography in DRAM

Positive and negative tone double patterning lithography for 50nm flash memory

New OPC verification method using die-to-database inspection

OPC accuracy enhancement through systematic OPC calibration and verification methodology for Sub-100nm node

OPC accuracy and process window verification methodology for sub-100-nm node