A chip-on-chip type semiconductor electronic component which meets requirement of further density increase of semiconductor integrated circuits is provided. A semiconductor device is also provided. In the chip-on-chip type semiconductor electronic component, the circuit surface of a first semiconductor chip and the circuit surface of a second semiconductor chip are arranged to face each other. A distance (X) between the first semiconductor chip and the second semiconductor chip is 50µm or less, and the shortest distance (Y) between the side surface of the second semiconductor chip and a first external electrode is 1mm or less. The semiconductor device using such semiconductor electronic component is also provided.

Semiconductor electronic component and semiconductor device using the same

The present invention provides polyimide polymer materials for passivating semiconductor wafers and methods for fabricating thereof. The present invention further provides a device that includes a semiconductor wafer and a passivating layer disposed on the surface of the wafer, wherein the passivating layer comprises such polyimide polymers.

Materials and methods for stress reduction in semiconductor wafer passivation layers

A package includes an internal package stacked upon a primary die. The package includes interconnection balls to allow the package to be electrically and physically connected to a mother board. The package is mounted to the mother board in a single operation thus minimizing labor and the associated manufacturing cost. Further, the package is tested and verified to be non-defective prior to mounting to the mother board.

Package in package (PiP)

According to one embodiment a method is provided including positioning and bonding a plurality of first semiconductor chips in a coplanar relation on a first substrate, laminating at least a plurality of second semiconductor chips on the first semiconductor chips, cutting the first substrate for separation into a discrete chip lamination, aligning an electrode pad provided on a surface of the discrete lamination with an electrode pad on a second substrate, and temporarily connecting the electrode pads on the lamination and the second substrate in an opposing relation to the first substrate, providing electrical connection between the electrode pads by a reflow process, flowing a liquid resin from the side of the first substrate towards the second substrate to seal the chip lamination and spaces between the chip lamination and the first and second substrate, and cutting the chip lamination to form a discrete device

Semiconductor device and manufacturing method of the same

A sealing material is provided which has sealing characteristics with low stress and high reliability upon mounting electronic parts on a board, and good repairablity after the sealing. The sealing material contains a heat-curable resin component and is characterized by ΔE/ΔT in a range of from 0.5 MPa/° C. to 30 MPa/° C. wherein ΔE/ΔT represents a ratio of change (ΔE) in storage elastic modulus (E) relative to a temperature change (ΔT) when the storage elastic modulus (E) is determined as the temperature is raised within a temperature range including a glass transition point (Tg) of the cured sealing material.

Sealing material and mounting method using the sealing material

Electronic packaging materials for use with Low-k dielectric-containing semiconductor devices are provided.

Gordon C. Fischer

Papers

Electronic packaging materials for use with low-k dielectric-containing semiconductor devices

Elektronsiche kapselungsmaterialien zur verwendung mit halbleiterbauelementen, die dielektrikum mit niedrigem k enthalten