A disclosed gaming machine has a plurality of “gaming peripherals,” each communicating with a master gaming controller via a standard peripheral interface such as the USB (Universal Serial Bus). Further, the gaming peripherals employ a standard peripheral controller and one or more specialized “peripheral devices” (e.g., the actual lights, bill validators, ticket printers, etc. that perform the specific functions of the gaming peripherals). Much of the hardware associated with the peripheral controller is identical from one gaming peripheral to the next. Only a portion of the peripheral controller hardware is specific to the different types of gaming peripherals.

Standard peripheral communication

A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

Programmable logic array integrated circuits

An integrated circuit computing device is comprised of a dynamically configurable Field Programmable Gate Array (FPGA). This gate array is configured to implement a RISC processor and a Reconfigurable Instruction Execution Unit. Since the FPGA can be dynamically reconfigured, the Reconfigurable Instruction Execution Unit can be dynamically changed to implement complex operations in hardware rather than in time-consuming software routines. This feature allows the computing device to operate at speeds that are orders of magnitude greater than traditional RISC or CISC counterparts. In addition, the programmability of the computing device makes it very flexible and hence, ideally suited to handle a large number of very complex and different applications.

Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor

A disclosed player tracking unit utilizes a memory arranged to store a plurality of different communication protocols allowing the player tracking unit to communicate with a plurality of different types of gaming machines and a plurality of different types of player tracking servers The player tracking unit may contain many different types of player tracking peripheral devices such as card readers, key pads, displays, bonus buttons and biometric input mechanisms The peripheral devices contained in the player tracking unit may be accessible to the master gaming controller on a gaming machine and may be utilized by the master gaming controller for other gaming applications The player tracking unit may be designed with a standard housing and standard device layout allowing the player tracking unit to fit in many different types of gaming machines with minimal modifications to the gaming machine or the player tracking unit

Universal player tracking system

Open architecture communication systems and methods are provided that allow flexible data transmission between gaming machines and other devices and nodes within a gaming machine network. The gaming machine and other devices employ a communication interface that sends and receives data via a common communication protocol and via common communication hardware. The communication interface and common communication protocol allow data transfer between gaming machines and other network nodes such as gaming service servers, despite the presence of different proprietary gaming machine functions and proprietary communication protocols and despite the presence of various proprietary hardware and proprietary communication protocols relied on by the servers.

Open architecture communications in a gaming network

A peripheral controller is described which is suitable for connecting a selected one of a plurality of peripheral devices to a computer system. The peripheral controller comprises programmable bidirectional line driver/receiver devices which can be operated in an input only mode, an output only mode or a bidirectional mode and which can be set into an appropriate mode by configuration control data sent from the computer system to the peripheral controller. The peripheral controller also includes a re-configurable logic array which can be configured under the control of the configuration control data to implement a particular interface required for the selected peripheral device. This increases the efficiency of use of a peripheral interface.

Uni and bi-directional signal transfer modes in peripheral controller and method of operating same

A configurable semi-conductor integrated circuit comprising an area thereof formed with a plurality of logic circuits at discrete sites or cells (cc) respectively defining a matrix array of cells. The matrix array of cells is subdivided at least into zones (each comprising a matrix array of cells) and further comprising a porting arrangement for each zone and a hierarchical routing resource structure comprising:- (i) global connection parts (G, X) having selectable connections with the porting arrangement of each zone, (ii) medium connection parts (M) extending from the porting arrangement and selectably connectable with at least some of the cells in a zone, and (iii) local direct connection paths comprising a restricted signal translation system. The application also describes a configurable semi-conductor integrated circuit comprising a matrix array of core cells (cc), each of the cells having a first simple function in common and at least one subsidiary function, there being at least two different subsidiary functions, the core cells being grouped in tiles comprising a matrix array of the core cells smaller than the whole array and wherein each tile has at least one of each different subsidiary functions and wherein the tiles of core cells are arranged so as to uniformly cover the array. Preferably there are fours cells to a tile and the preferred subsidiary function are:- wired-OR, XOR, D-type flip flop and latch function. The above features are preferably combined to produce a particularly advantageous construction of configurable semi-conductor integrated circuit.

Configurable logic array.

A semi-conductor integrated circuit, as made, comprises a plurality of cells, each cell having a plurality of resources which comprise storage/programming resources and functional resources. The functional resources comprise routing resources and/or logic function resources according to the cell type. The resources available to one cell are augmented by utilising resources from at least one other cell, without preventing the donor cell from functioning independently. An hierarchical routing structure is disposed in successive layers. A matrix array of cells divided into zones has a zone porting arrangement for each zone. The successive layers of routing resource comprise: zone interconnect comprising local direct connection paths connecting at least some of the cells with some other cells; and medium connection paths extending from the zone porting arrangement and selectably connectable with at least some of the cells in a zone; and global connection paths having selectable connections with the zone porting arrangement of each zone; and ```one or more further successive levels of routing resource.

Semi-conductor integrated circuit

A semi-conductor integrated circuit, as made, comprises an area thereof formed with a plurality of cells cc, each cell having a plurality of resources which comprise storage/programming resources and functional resources. The functional resources comprise at least one of routing resources and logic function resources according to the cell type. As made each cell has a finite number of resources in it. According to one aspect, the resources available to one cell are augmented by utilising resources from at least one other cell. This is achieved without preventing the donor cell from functioning independently. Also described is a hierarchical routing structure disposed in successive layers. The cells are disposed in a matrix array of cells divided into zones. There is a plurality of zones in the array and a zone porting arrangement for each zone. According to another aspect of the invention the successive layers of routing resource comprises zone interconnect comprising local direct connection paths connecting at least some of the cells with some other cells, and medium connection paths extending from the zone porting arrangement and selectably connectable with at least some of the cells in a zone; and global connection paths having selectable connections with the zone porting arrangement of each zone; and further comprising one or more further successive levels of routing resource having a respective porting arrangement to connect that level of routing resource with the preceding level of routing resource.

Gordon Stirling Work

Papers

Uni and bi-directional signal transfer modes in peripheral controller and method of operating same

Configurable logic array.

Semi-conductor integrated circuit

A semi-conductor integrated circuit