During the manufacturing process, electronic devices are thoroughly tested for defects. However, testing for well-known fault models, such as stuck-at and transition delay, may not be sufficient for an effective performance screening. In modern devices, Design-for-Testability features embedded at design time can allow the tester to apply stimuli and measure different critical parameters. We propose to use some of these structures, namely the speed monitors, to predict the maximum operating speed, and screen out under-performing devices. We design a complete methodology, from the extraction of robust labels, through a machine-learning algorithm, down to a post-processing step, able to meet the quality standards imposed by industry. Experimental results using real production data demonstrate the feasibility of the approach.

Machine Learning based Performance Prediction of Microcontrollers using Speed Monitors

In the paradigm of stochastic computing, arithmetic functions are computed on randomized bit streams. The method naturally and effectively tolerates very high clock skew. Exploiting this advantage, this paper introduces polysynchronous clocking, a design strategy in which clock domains are split at a very fine level. Each domain is synchronized by an inexpensive local clock. Alternatively, the skew requirements for a global clock distribution network can be relaxed. This allows for a higher working frequency and so lower latency. The benefits of both approaches are quantified. Polysynchronous clocking results in significant latency, area, and energy savings for wide variety of applications.

Polysynchronous Clocking: Exploiting the Skew Tolerance of Stochastic Circuits

The digital designs operating in sub/near-threshold region are susceptible to timing errors due to the extreme impact of process, voltage, and temperature (PVT) variations. This paper proposes a new error-detecting latch (EDL) to mitigate the impact of PVT variations. The proposed EDL is a single-phase clocked design, which significantly reduces the clock power consumption of the design. The proposed EDL follows a merged and shared architecture of two latches along with an XNOR gate, which leads to a compact layout of EDL. The post-layout simulations in an industrial 28 nm CMOS technology node, show a minimum clock power savings of 31%, average power savings of 16%, and reduction in leakage power by 23% in comparison to the state-of-the-art EDLs at 0.4 V. The 10K rigorous Monte-Carlo simulations across the supply voltage range of 0.23 V - 0.8 V and clock frequency range of 1.6 MHz - 70 MHz shows that the proposed EDL is tolerant to leakage-induced false errors and glitches. SSEDL is robust to process variations even with minimum-sized transistors.

Design and Analysis of Leakage-Induced False Error Tolerant Error Detecting Latch for Sub/Near-Threshold Applications

Metastability immune and area efficient error masking flip-flop for timing error resilient designs

In safety-critical applications, microcontrollers must satisfy strict quality constraints and performances in terms of $F_{\max}$, that is, the maximum operating frequency. It has been demonstrated that data extracted from on-chip speed monitors can model the $F_{\max}$ of integrated circuits by means of machine learning models, and that those models are suitable for the performance screening process. However, while acquiring data from these monitors is quite an accurate process, the labelling is time-consuming, costly, and may be subject to different measurements errors, impairing the final quality. This paper presents a methodology to cope with anomalous and noisy data in the context of the multi-label regression problem of microcontroller performance screening. We used outlier detection based on Inter Quartile Range (IQR) and Z-score and imputation techniques to detect errors in the labels and to avoid to drop incomplete samples, building higher-quality training set for our models, optimizing the devices characterization phase. Experiments showed that the proposed methodology increases the performance of existing models, making them more robust. These techniques permitted us to use a significantly smaller number of samples (about one third of the devices available for characterization), thus making the costly data acquisition process more efficient.

Microcontroller Performance Screening: Optimizing the Characterization in the Presence of Anomalous and Noisy Data

Timing error predictors have a strong potential to reduce the worst case timing margins by monitoring timing slack of a design. However, these timing error predictors incur substantial amount of silicon area and power which limit the overall benefits in the system level. This paper presents a low overhead warning flip-flop (FF), which predicts setup time violations. It consists of a delay buffer and a warning generator along with a conventional master-slave FF. Low overhead FF can be designed by exploiting the concept of charge sharing to implement the warning generator. As the warning generator requires only seven transistors to predict the timing violation, the proposed warning FF occupies 30% less area and consumes 27% less power compared to the state-of-the-art timing error predictors. A test chip is fabricated using the proposed FF in a 130-nm CMOS technology to verify the functionality of the proposed warning FF in dynamic voltage and frequency scaling applications. Measurement results from the test chip show that a performance improvement of 44% can be achieved at a supply voltage of 0.9 V by employing the proposed technique compared to the worst case design. For a typical chip, the power consumption can be reduced by 36% compared to the worst case design.

Low Overhead Warning Flip-Flop Based on Charge Sharing for Timing Slack Monitoring

In this paper, two timing error masking flip-flops have been proposed, which are immune to metastability. The proposed flip-flops exploit the concept of either delayed data or pulse based approach to detect timing errors. The timing violations are masked by passing direct data instead of master latch output to slave latch. Simulation results show that the proposed flip-flops such as type-A and type-B reduce the error masking latency up to 23% and 42% respectively in typical process corners and increase the effective timing error monitoring window compared to state of the art metastable immune flip-flops [14]. The proposed flip-flops can be used in dynamic voltage and frequency scaling (DVFS) applications. A 16-bit adder is implemented to evaluate the functionality of the proposed flip-flops in DVFS frame work and the simulation results show that the adder using the proposed flip-flop can reduce up to 48% power consumption or improve the performance up to 50% in typical process corners compared to conventional worst case design.

A Metastability Immune Timing Error Masking Flip-Flop for Dynamic Variation Tolerance

Error detectors/predictors are inevitable for any power and performance constrained designs. Dynamic voltage and frequency scaling can be efficiently implemented using these error detectors/predictors. In this work, we propose a new area and power efficient error predictor for dynamic voltage and frequency scaling application. In the proposed error predictor, the edge of delayed data of master latch is observed in the high phase of the clock to flag a warning signal. The warning signal determines the point of reduction in the supply voltage without any system failure. Compared to pulse-based error predictor, our timing error predictor consumes 17% less power under 100% switching activity and requires 27% less additional area overhead. The functionality of the proposed FF is tested by implementing ISCAS89 benchmark circuits, 16-bit adder, and 16-bit multiplier. A fully automated insertion flow is adopted to implement the block level designs. Using the proposed FF in a block level implementation shows that it can save power up to 33% in the typical corner compared to conventional worst case design.

Govinda Sannena

Papers

Low Overhead Warning Flip-Flop Based on Charge Sharing for Timing Slack Monitoring

A Metastability Immune Timing Error Masking Flip-Flop for Dynamic Variation Tolerance

Metastability immune and area efficient error masking flip-flop for timing error resilient designs

Area and Power-Efficient Timing Error Predictor for Dynamic Voltage and Frequency Scaling Application