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Design Of Analog Cmos Integrated Circuits

In this paper, we propose a low complex architectural design for hearing aid applications. In this, we recast the hearing aid using distributed arithmetic (DA), which enables the implementation of hearing aid without multipliers. The design is based on the distributed arithmetic based formulation of it. It is further shown that high order filters, which are required to implement high-speed hearing aid can be realized using only look-up-tables and shift-accumulate operations. A novel approach was proposed to replace the decimation filter of a hearing aid using multiplier less architecture with a single DA unit. By proper initialization, it is shown that low complexity hearing aid architecture can be obtained. The proposed distributed arithmetic architecture is implemented in ASIC SAED 90 nm technology. The application of hearing aid is implemented in Matlab Simulink and Xilinx system generator tool. The obtained results show $$20\%$$ less area delay product and $$40\%$$ less power delay product when compared with the existing architecture.

Low power area efficient adaptive FIR filter for hearing aids using distributed arithmetic architecture

In this paper an efficient implementation of decision feed back equalizer (DFE) is carried out using novel memory less distributed arithmetic (NMLDA) filter. In wireless transmission systems, DFEs are used to mitigate the inter-symbol interference (ISI). The ISI is occurred due to multi-path propagation of the transmitted signal. High data rate systems demand higher order filters in DFE architectures which increase complexity in hardware design. In our proposed NMLDA design, we have used multiplexers and enhanced compressor adders in place of memory unit and conventional adders. The proposed design occupies lower area and gives higher throughput, when compared to MAC based filter and all other memory based DA filter architectures. By using proposed NMLDA based DFE, the ISI errors in transmission signal, will be minimized and the performance of the transmission system will be enhanced. We have synthesized the NMLDA of 32-tap, 16-tap, 8-tap and 4-tap filters and implemented them on FPGA device. The proposed design has nearly 70% less number of logical elements than OBC DA and 50% less than MDA and offers better throughput than the existing designs when implemented on Altera Cyclone III EP3C55F484C6.

High speed and low area decision feed-back equalizer with novel memory less distributed arithmetic filter

This paper elucidates the system construct of DA-FIR filter optimized for design of distributed arithmetic (DA) finite impulse response (FIR) filter and is based on architecture with tightly coupled co-processor based data processing units. With a series of look-up-table (LUT) accesses in order to emulate multiply and accumulate operations the constructed DA based FIR filter is implemented on FPGA. The very high speed integrated circuit hardware description language (VHDL) is used implement the proposed filter and the design is verified using simulation. This paper discusses two optimization algorithms and resulting optimizations are incorporated into LUT layer and architecture extractions. The proposed method offers an optimized design in the form of offers average miminimizations of the number of LUT, reduction in populated slices and gate minimization for DA-finite impulse response filter. This research paves a direction towards development of bio inspired computing architectures developed without logically intensive operations, obtaining the desired specifications with respect to performance, timing, and reliability.

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Design and implementation of DA FIR filter for bio-inspired computing architecture

Daily attendance marking is a common and important activity in schools and colleges for checking the performance of students. Manual Attendance maintaining is difficult to process, especially for a large group of students. Some automated systems developed to overcome these difficulties, have drawbacks like cost, fake attendance, accuracy, intrusiveness. To overcome these drawbacks, there is a need for a smart and automated attendance system. Traditional face recognition systems employ methods to identify a face from the given input but the results are not usually accurate and precise as desired. The system described in this we aim to deviate from such traditional systems and introduce a new approach to identify a student using a face recognition system, the generation of a facial Model. This describes the working of the face recognition system that will be deployed as an Automated Attendance System in a classroom environment. The proposed smart classroom system was tested for a classroom with 20 students at K L University Andhra Pradesh, Vijayawada, India and we got the experimental results to demonstrate the train and test accuracy of 97.67% and 96.66%, respectively. In this paper we selecting of the face recognition and detection giving result using Python language in PYCHARM tool. This requires high end specifications of a system in order to get better results. It won’t run on all the small specification systems. So, this can run only a small database and compare them with the face required.

Computer vision based classroom attendance management system-with speech output using LBPH algorithm

Digital signal processing (DSP) systems are becoming popular with the emergence of artificial intelligence and machine learning based applications. Residue number system is one of most sought representation for implementing the high speed DSP systems. This paper presents an efficient implementation of memory less distributed arithmetic (MLDA) architecture in finite impulse response filter with residual number system. The input data and filter coefficients of MLDA are in residue number form and the output data from MLDA is converted into binary form using Chinese remainder theorem. In addition, compressor adders are used to reduce the area. For real time validation, the proposed design has been simulated and synthesized in application specific integrated circuit platform using synopsis design compiler with CMOS 90 nm technology. The results show that the proposed design has very high computation speed with total delay of only 20 ns and occupies 20% less area in comparison with the existing designs.

ASIC implementation of distributed arithmetic based FIR filter using RNS for high speed DSP systems

This paper presents a brief information on the ASIC implementation of adaptive finite impulse response (FIR) filters based on pipelined distributed arithmetic (DA) architecture. The pipelined sum of partial products of input samples is stored in the lookup table of the DA. The area of the proposed design is reduced by replacing the adder of the shift accumulation unit with the carry-save adder. The throughput rate of the design is increased by having fast clock to the carry-save adder and slow clock to the remaining circuit. The proposed design is implemented in Synopsys 90 nm CMOS technology. The area delay product (ADP), minimum cycle period (MCP), and energy per sample are reduced when compared with the conventional DA-based architectures.

ASIC Implementation of Low Power, Area Efficient Adaptive FIR Filter Using Pipelined DA

Low Power, Low Area Adaptive Finite Impulse Response Filter Based on Memory Less Distributed Arithmetic

Power consumption plays a crucial role in the design of portable wireless communication devices, as it has a direct influence on the battery weight and volume required for operation. This article p...

ASIC Implementation of Linear Equalizer Using Adaptive FIR Filter

In this paper, we proposed a Coordinate Rotation Digital Computer (CORDIC) algorithm for efficient hardware implementation of mathematical functions which can be carried out in a wide variety of ways for many digital signal processing applications. The CORDIC is a single unified algorithm for calculating many elementary functions such as trigonometric, hyperbolic, logarithmic function, exponential functions, multiplication, division, and so on. In this paper, a novel low power, low area, and high throughput fixed-point CORDIC algorithms are proposed. The standard CORDIC is also implemented for comparing the synthesis results. The proposed architecture scaling has been done using low area and low-power Scale Factor Correction Unit (SFCU). A low ADP SQRT-CSLA based ADD/SUB unit is proposed to overcomed the disadvantages of the basic ADD/SUB unit used in the standard CORDIC. The ROM lookup table size is also reduced to half. Extensive simulations are performed to verify the functionality. The standard and proposed CORDIC architectures are simulated in cadence NC launch and synthesized in cadence RC tool using TSMC GPDK 45 nm technology and area, power, and delay are calculated. The area and power consumption of the proposed CORDIC architecture are less when compared with standard CORDIC design.

Grande Naga Jyothi

Papers

ASIC implementation of distributed arithmetic based FIR filter using RNS for high speed DSP systems

ASIC Implementation of Low Power, Area Efficient Adaptive FIR Filter Using Pipelined DA

Low Power, Low Area Adaptive Finite Impulse Response Filter Based on Memory Less Distributed Arithmetic

ASIC Implementation of Linear Equalizer Using Adaptive FIR Filter

ASIC Implementation of Fixed-Point Iterative, Parallel, and Pipeline CORDIC Algorithm.