In this paper, we propose a low complex architectural design for hearing aid applications. In this, we recast the hearing aid using distributed arithmetic (DA), which enables the implementation of hearing aid without multipliers. The design is based on the distributed arithmetic based formulation of it. It is further shown that high order filters, which are required to implement high-speed hearing aid can be realized using only look-up-tables and shift-accumulate operations. A novel approach was proposed to replace the decimation filter of a hearing aid using multiplier less architecture with a single DA unit. By proper initialization, it is shown that low complexity hearing aid architecture can be obtained. The proposed distributed arithmetic architecture is implemented in ASIC SAED 90 nm technology. The application of hearing aid is implemented in Matlab Simulink and Xilinx system generator tool. The obtained results show $$20\%$$ less area delay product and $$40\%$$ less power delay product when compared with the existing architecture.

Low power area efficient adaptive FIR filter for hearing aids using distributed arithmetic architecture

Bandgap reference using 2 BJT devices are well explored in the literature. Usually, less number of BJT's would reduce the cost of the chip in modern CMOS technologies. A single BJT based reference was discussed here. V BE of the BJT has been used as CTAT voltage and a CMOS differential pair offset voltage based PTAT generation circuit used to generate zero temp coefficient reference. A prototype was developed in 45nm TSMC CMOS technology and post-layout simulationswere performed. Designed for a nominal voltage of 525mV with 10.2ppm/°C temperature coefficient. Its supply sensitivity is 0.4% and works with 1V power supply. The proposed solution consumes $51.8\mu \mathrm{W}$ power from 1V power supply and occupies $2478\ \mu \mathrm{m}^{2}$ silicon area.

A Single BJT 10.2 ppm/°C Bandgap Reference in 45nm CMOS Technology

This work is a demonstration of circuit optimization using Taguchi Design of Experiments. Cross coupled channel length modulation OTA has been considered for optimization. This optimization technique uses the concept of Signal to Noise Ratio (SNR) and Analysis of Variance (ANOVA) to predict which independent variable controls the performance of the circuit. Bias current, channel width and channel length of input transistors have been chosen to optimize the circuit performance. The obtained parameters for optimum performance from this method are verified by simulating the circuit using UMC 0.18  μ m CMOS technology. The simulation results obtained are pretty close to the predicted solution from ANOVA. From simulation results, transconductance, power consumption, percentage total harmonic distortion, linearity range and DC gain of the proposed OTA are 24.63  nS , 1.026  μ W , 0.347 % , 1.09  V , and 54.88  dB respectively. The proposed optimized circuit, therefore, can be utilized in biomedical applications.

Taguchi DoE and ANOVA: A systematic perspective for performance optimization of cross-coupled channel length modulation OTA

Digital signal processing (DSP) systems are becoming popular with the emergence of artificial intelligence and machine learning based applications. Residue number system is one of most sought representation for implementing the high speed DSP systems. This paper presents an efficient implementation of memory less distributed arithmetic (MLDA) architecture in finite impulse response filter with residual number system. The input data and filter coefficients of MLDA are in residue number form and the output data from MLDA is converted into binary form using Chinese remainder theorem. In addition, compressor adders are used to reduce the area. For real time validation, the proposed design has been simulated and synthesized in application specific integrated circuit platform using synopsis design compiler with CMOS 90 nm technology. The results show that the proposed design has very high computation speed with total delay of only 20 ns and occupies 20% less area in comparison with the existing designs.

ASIC implementation of distributed arithmetic based FIR filter using RNS for high speed DSP systems

In this paper an efficient implementation of decision feed back equalizer (DFE) is carried out using novel memory less distributed arithmetic (NMLDA) filter. In wireless transmission systems, DFEs are used to mitigate the inter-symbol interference (ISI). The ISI is occurred due to multi-path propagation of the transmitted signal. High data rate systems demand higher order filters in DFE architectures which increase complexity in hardware design. In our proposed NMLDA design, we have used multiplexers and enhanced compressor adders in place of memory unit and conventional adders. The proposed design occupies lower area and gives higher throughput, when compared to MAC based filter and all other memory based DA filter architectures. By using proposed NMLDA based DFE, the ISI errors in transmission signal, will be minimized and the performance of the transmission system will be enhanced. We have synthesized the NMLDA of 32-tap, 16-tap, 8-tap and 4-tap filters and implemented them on FPGA device. The proposed design has nearly 70% less number of logical elements than OBC DA and 50% less than MDA and offers better throughput than the existing designs when implemented on Altera Cyclone III EP3C55F484C6.

High speed and low area decision feed-back equalizer with novel memory less distributed arithmetic filter

In this paper a microwatt low voltage bandgap reference suitable for the bio-medical application. The Present technique relies on the principle of generating CTAT and PTAT without using any (Bipolar Junction Transistor) BJT and adding them with a proper scaling factor for minimal temperature sensitive reference voltage. Beta multiplier reference circuit has been explored to generate CTAT and PTAT. Implemented in 45nm CMOS technology and simulated with Spectre. Simulation results shows that the proposed reference circuit exhibits 1.2% variation at nominal 745mV output voltage. The circuit consumes 16uW from 0.8V supply and occupying 0.004875mm2 silicon area.

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A Microwatt Low Voltage Bandgap Reference for Bio-medical Applications

Finite impulse response (FIR) filter is an influential block in various signal processing applications. The complexities in VLSI implementation of FIR filters is dominated by the number of multiply and accumulate (MAC) operations. Distributed Arithmetic (DA) is an alternative technique where the MAC operations can be replaced by a series of look-up tables and addition operations. FIR filter based on DA are computationally efficient because of high degree of mechanization involved in the implementation of MAC operations using DA. Many reconfigurable and non-reconfigurable FIR filter architectures can be developed using DA. This paper reviews the existing FIR filter architectures based on DA. LUT based DA and LUT-less DA are the significant methods in the implementation of non-reconfigurable filters. This brief summarizes the area and power reports of the existing non-reconfigurable FIR filter architectures based on both LUT based DA and LUT-less DA. One dimensional and two dimensional systolic DA based architectures for FIR filter implementation are also briefed. DA based adaptive FIR techniques are explained. This paper presents the comparative results of FIR and adaptive FIR filter architectures in terms of area, power, area-delay product, minimum cycle period and energy per sample. This survey can form a basis for further research on DA based FIR filter architectures.

Distributed arithmetic architectures for FIR filters-A comparative review

In this paper a low power, high gain self bias opamp suitable for biomedical applications has been described. A novel trans conductance boosting technique is introduced without having any additional power consumption. A simple technique of biasing the opamp has been introduced for very low offset and without having any requirement for external reference circuit. A prototype of two stage amplifier design presented to verify the proposed technique and described its robustness across PVT variations by showing simulation results. The design is implemented in 45nm CMOS technology and simulated with Spectre. Simulation results show that the proposed opamp exhibits FOM of 625 and 2 times better than state of art. The circuit consumes 26uW from 1.5V supply and occupying 0.00282mm2 silicon area.

A bio-medical compatible self bias opamp in 45nm CMOS technology

In this paper, a PVT insensitive variable gain amplifier (VGA) has been proposed which is suitable for bio-medical neural recording. Proposed amplifier delivers an appreciably enhanced performance over that of existing technique. Constant Gm bias stability is described in the frequency domain. Noise problems with the existing technique are described qualitatively. A prototype circuit has been implemented in 65nm CMOS technology and simulated with Spectre. 2–25dB gain programmable range was achieved across PVT and 0.3dB standard deviation. 1.2uV integrated RMS noise was achieved. The circuit consumes 0.5mA from the 1.5V supply voltage and occupies 4500um2 silicon area.

Sriadibhatla Sridevi

Papers

A Microwatt Low Voltage Bandgap Reference for Bio-medical Applications

Distributed arithmetic architectures for FIR filters-A comparative review

High speed and low area decision feed-back equalizer with novel memory less distributed arithmetic filter

A bio-medical compatible self bias opamp in 45nm CMOS technology

A PVT insensitive programmable amplifier for biomedical applications