G
Gu-Yeon Wei
Researcher at Harvard University
Publications - 216
Citations - 9743
Gu-Yeon Wei is an academic researcher from Harvard University. The author has contributed to research in topics: Deep learning & Computer science. The author has an hindex of 46, co-authored 198 publications receiving 8154 citations. Previous affiliations of Gu-Yeon Wei include Stanford University.
Papers
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Proceedings ArticleDOI
System level analysis of fast, per-core DVFS using on-chip switching regulators
TL;DR: It is concluded that on-chip regulators can significantly improve DVFS effectiveness and lead to overall system energy savings in a CMP, but architects must carefully account for overheads and costs when designing next-generation DVFS systems and algorithms.
Journal ArticleDOI
Minerva: enabling low-power, highly-accurate deep neural network accelerators
Brandon Reagen,Paul N. Whatmough,Robert Adolf,Saketh Rama,Hyunkwang Lee,Sae Kyu Lee,José Miguel Hernández-Lobato,Gu-Yeon Wei,David Brooks +8 more
TL;DR: Minerva as mentioned in this paper proposes a co-design approach across the algorithm, architecture, and circuit levels to optimize DNN hardware accelerators, and shows that fine-grained, heterogeneous dataatype optimization reduces power by 1.5× and aggressive, inline predication and pruning of small activity values further reduces power.
Proceedings ArticleDOI
Process Variation Tolerant 3T1D-Based Cache Architectures
TL;DR: A range of cache refresh and placement schemes that are sensitive to retention time are proposed, and it is shown that most of the retention time variations can be masked by the microarchitecture when using these schemes.
Proceedings ArticleDOI
Profiling a warehouse-scale computer
Svilen Kanev,Juan Pablo Darago,Kim Hazelwood,Parthasarathy Ranganathan,Tipp Moseley,Gu-Yeon Wei,David Brooks +6 more
TL;DR: A detailed microarchitectural analysis of live datacenter jobs, measured on more than 20,000 Google machines over a three year period, and comprising thousands of different applications finds that WSC workloads are extremely diverse, breeding the need for architectures that can tolerate application variability without performance loss.
Journal ArticleDOI
Aladdin: a Pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures
TL;DR: Aladdin is presented, a pre-RTL, power-performance accelerator modeling framework and its application to system-on-chip (SoC) simulation and provides researchers an approach to model the power and performance of accelerators in an SoC environment.