Gu-Yeon Wei

TL;DR: This paper presents a maximum a posteriori probability (MAP) detector, based on a forward-only algorithm that can achieve high throughputs and can approach performance close to the channel capacity limit.

TL;DR: EdgeBERT is presented, an in-depth and principled algorithm and hardware design methodology to achieve minimal latency and energy consumption on multi-task NLP inference and enables fully on-chip inference acceleration of NLP workloads with 5.2x and 157x lower energy than that of an un-optimized accelerator and CUDA adaptations on an Nvidia Jetson Tegra X2 mobile GPU, respectively.

TL;DR: A 16nm programmable accelerator for unsupervised probabilistic machine perception tasks that performs Bayesian inference on Probabilistic models mapped onto a 2D Markov Random Field, using MCMC is described.

TL;DR: In this paper, a post-fabrication tuning knob called voltage interpolation is proposed to mitigate the performance and power overheads of process variation in advanced fabrication technologies, which can be used to mitigate overhead arising from random and correlated within-die process variations.

TL;DR: The performance and system reliability constraints that are key impediments to VLV are discussed and the associated trade-offs across power, performance and reliability are helpful in inferring the optimal operational voltage-frequency point.