Showing papers by "Guanghui He published in 2017"

High-linearity phase interpolator

Abstract: The invention provides a high-linearity phase interpolator. The high-linearity phase interpolator comprises a load circuit, a differential pair set, a main current source bias array and two auxiliary current source bias arrays; the load circuit is connected to an equipotential end; the differential pair set is connected to the load circuit, a first signal input end, a second signal input end, a third signal input end and a fourth signal input end; the main current source bias array is connected to the differential pair set, a quadrant control signal input end, a first phase control signal input end and a first bias voltage input end; and the two auxiliary current source bias arrays are separately connected to the main current source bias array, a second phase control signal input end and a second bias voltage input end. By means of the high-linearity phase interpolator provided by the invention, high-linearity phase output can be obtained.

A hardware-friendly hierarchical HEVC motion estimation algorithm for UHD applications

Abstract: High Efficiency Video Coding (HEVC) standard has a superior video compression rate compared with previous H.264/AVC. At the same time, Ultra-high-definition (UHD) video applications are becoming a reality under the development of the display technology. In this paper, a hardware-friendly multi-layer HEVC motion estimation (ME) algorithm for UHD applications are proposed. To keep the computational regularity of the traditional full-search (FS) ME algorithm as well as reduce the computational complexity of ME in a large search range (SR), the basic layer of the proposed algorithm is to combine FS scheme in a core area with downsampling search scheme in a large peripheral area. Moreover, the finer layer of the algorithm employs a hexagon search scheme to perform further ME around the optimal match point generated by the basic layer. Integrating the proposed algorithm into the HM 15.0, experimental results show that our hardware-friendly algorithm can achieve 97.8% of computations reduction while only 0.77% of BD-rate loss on average. Consequently, the proposed algorithm is feasible for HEVC ME hardware design for UHD applications.

Short path padding with multiple-V t cells for wide-pulsed-latch based circuits at ultra-low voltage

Abstract: This paper presents a short path padding technique for wide-pulsed-latch based circuit design in near/sub-threshold (V t ) regime. To reduce the additional hardware cost, multiple-V t buffer cells are used to pad the short paths to avoid hold time violations. To reduce the runtime of the padding algorithm further, step-by-step based and path group based short path padding schemes are proposed. Employing the integer linear programming (ILP) solver, an automatic short path padding software is developed. Experimental results show that our proposed short path padding technique can reduce 52.3% hardware padding cost on average. Furthermore, the runtime of padding software is reduced 79.6%, 74.95% and 80.88%, by using the step-by-step based, path group based and the hybrid scheme, respectively. In consequence, this technique supports up to a wide pulse of 1/3 cycle time in the pulsed-latch pipelines to enable a large time-borrowing capability and tolerance of variations.