Power module packaging technologies have been experiencing extensive changes as the novel silicon carbide (SiC) power devices with superior performance become commercially available. This article presents an overview of power module packaging technologies in this transition, with an emphasis on the challenges that current standard packaging face, requirements that future power module packaging needs to fulfill, and recent advances on packaging technologies. The standard power module structure, which is a widely used current practice to package SiC devices, is reviewed, and the reasons why novel packaging technologies should be developed are described in this article. The packaging challenges associated with high-speed switching, thermal management, high-temperature operation, and high-voltage isolation are explained in detail. Recent advances on technologies, which try to address the limitations of standard packaging, both in packaging elements and package structure are summarized. The trend toward novel soft-switching power converters gave rise to problems regarding package designs of unconventional module configuration. Potential applications areas, such as aerospace applications, introduce low-temperature challenges to SiC packaging. Key issues in these emerging areas are highlighted.

A Review of SiC Power Module Packaging Technologies: Challenges, Advances, and Emerging Issues

Wide-bandgap (WBG) power semiconductor devices have become increasingly popular due to their superior characteristics compared to their Si counterparts. However, their fast switching speed and the ability to operate at high frequencies brought new challenges, among which the electromagnetic interference (EMI) is one of the major concerns. Many works investigated the structures of WBG power devices and their switching performance. In some cases, the conductive or radiated EMI was measured. However, the EMI-related topics, including their influence on noise sources, noise propagation paths, EMI reduction techniques, and EMC reliability issues, have not yet been systematically summarized for WBG devices. In this article, the literature on EMI research in power electronics systems with WBG devices is reviewed. Characteristics of WBG devices as EMI noise sources are reviewed. EMI propagation paths, near-field coupling, and radiated EMI are surveyed. EMI reduction techniques are categorized and reviewed. Specifically, the EMI-related reliability issues are discussed, and solutions and guidelines are presented.

A Survey of EMI Research in Power Electronics Systems With Wide-Bandgap Semiconductor Devices

A large number of factors such as the increasingly stringent pollutant emission policies, fossil fuel scarcity and their price volatility have increased the interest towards the partial or total electrification of current vehicular technologies. These transition of the vehicle fleet into electric is being carried out progressively. In the last decades, several technological milestones have been achieved, which range from the development of basic components to the current integrated electric drives made of silicon (Si) based power modules. In this context, the automotive industry and political and social agents are forcing the current technology of electric drives to its limits. For example, the U.S Department of Energy’s goals for 2020 include the development of power converter technologies with power densities higher than 14.1 kW/kg and efficiencies greater than 98%. Additionally, target price of power converters has been set below $3.3/kW. Thus, these goals could be only achieved by using advanced semiconductor technologies. Wide-bandgap (WBG) semiconductors, and, most notably, silicon carbide (SiC) based power electronic devices, have been proposed as the most promising alternative to Si devices due to their superior material properties. As the power module is one of the most significant component of the traction power converter, this work focuses on an in-deep review of the state of the art concerning such element, identifying the electrical requirements for the modules and the power conversion topologies that will best suit future drives. Additionally, current WBG technology is reviewed and, after a market analysis, the most suitable power semiconductor devices are highlighted. Finally, this work focuses on practical design aspects of the module, such as the layout of the module and optimum WBG based die parallelization, placement and Direct Bonded Copper (DBC) routing.

Power module electronics in HEV/EV applications: New trends in wide-bandgap semiconductor technologies and design aspects

Featuring higher switching speed and lower losses, the silicon carbide mosfet s (SiC mosfet s) are widely used in higher power density and higher efficiency power electronic applications as a new solution. However, the increase of the switching speed induces oscillations, overshoots, electromagnetic interference (EMI), and even additional losses. In this paper, a novel active gate driver (AGD) for high-power SiC mosfet s is presented to fully utilize its potential of high-speed characteristic under different operation temperatures and load currents. The principle of the AGD is based on drive voltage decrement during the voltage and current slopes since high dV/dt and dI/dt are the source of the overshoots, oscillations, and EMI problems. In addition, the optimal drive voltage switching delay time has been analyzed and calculated considering a tradeoff between switching losses and switching stresses. Compared to conventional gate driver with fixed drive voltage, the proposed AGD has the capability of suppressing the overshoots, oscillations, and reducing losses without compromising the EMI. Finally, the switching performance of the AGD was experimentally verified on 1.2 kV/300 A and 1.7 kV/300 A SiC mosfet s in double pulse test under different operation temperatures and load currents. In addition, an EMI discussion and cost analysis were realized for AGD.

A Novel Active Gate Driver for Improving Switching Performance of High-Power SiC MOSFET Modules

Silicon carbide (SiC) power modules are promising for high-power applications because of the high breakdown voltage, high operation temperature, low ON-resistance, and fast switching speed However, the large parasitic inductance in existing package designs results in compromised performance, ie, long blanking time in the desaturation protection scheme and large overvoltage spikes during the switching transient Consequently, the benefits of SiC devices are often not fully utilized in practical applications This paper deals with these two issues and aims at improving the electrical performance of the existing SiC module package Specifically, a package design with Kelvin drain-to-source connection is first proposed to minimize the blanking time More than 99% reduction of blanking time is achieved experimentally compared to the conventional package design Second, a low parasitic inductance package with double-side cooling is proposed to allow the fast switching speed of SiC devices without sacrificing the thermal performance A power loop inductance of 163 nH is realized from Q3D simulation Verified by the experiment, more than 60% reduction of power loop inductance is achieved in comparison to a previously designed baseline module At 0- $\Omega $ external gate resistance, the turn-off voltage spike is less than 9% of the dc-link voltage under the rated load condition

Electrical Performance Advancement in SiC Power Module Package Design With Kelvin Drain Connection and Low Parasitic Inductance

A new 3-D power module dedicated to SiC mosfet is presented. It is based on printed circuit board embedded die technology and is compared with a standard power module. After considering the characteristics that contribute to optimal switching performances from the packaging point of view, both modules are characterized in terms of switching behavior and electromagnetic interference emissions. The results show better performances of the 3-D embedded die module with stray inductances below 2 nH and two times less common mode noise.

Optimized Power Modules for Silicon Carbide mosfet

A new three dimensional package based on Printed Circuit Board (PCB) embedded die technology is presented in this paper. The package takes advantage of the Power Chip On Chip (PCOC) concept, where commutation cell is housed within the bus bar, allowing a very low inductance design for the package of up to 0.25 nH. Two key design challenges with the package relate to the layout and the thermal management. Thus, a parallelization technique enabling impedance balancing is developed for the layout and validated using four parallel Silicon Carbide (SiC) MOSFETs. Gate circuit is carefully designed allowing low inductive behavior and low electromagnetic coupling. Finally, the thermal management of the module is studied and die attach with direct copper filled vias is validated.

Silicon carbide power chip on chip module based on embedded die technology with paralleled dies

An Integrated Power Board technology was used to construct a 3D power module. This packaging is suitable for use of WBG devices as it reduces the inductive parasitics to the strict minimum, with a 2nH loop inductance in our 1.2kV/80A SiC prototype using SiC MOSFETs. The packaging presents virtually no parasitics or necessity for slowing down the commutation, which is oscillation-free. The conducted emissions of the 3D module are more than halved in comparison to those of a bespoke wire-bonded, EMI-optimised module.

Optimized power modules for silicon carbide MOSFET

Le developpement d'un packaging dedie aux transistors a grand gap (SiC et GaN) est un point clef pour tirer pleinement profit de leurs caracteristiques remarquables. Un packaging en trois dimensions, base sur un procede de fabrication des circuits imprimes, est presente dans cet article. Une cellule de commutation a base de MOSFET SiC est developpe avec une inductance parasite de seulement 0.25nH. De plus, les interconnexions electriques du module sont realisees sans brasures ni fil de bonding. Un module 3D est fabrique puis valide experimentalement. Des caracterisations electriques statiques et dynamiques sont realisees et valident electriquement le concept « Power Chip On Chip » avec un procede de fabrication de circuit imprime.

https://hal.archives-ouvertes.fr/hal-01361591/document

Packaging 3D pour MOSFET en carbure de silicium

The design of highly integrated converter is more than ever a hot topic in the power electronic world. Integration also brings new challenges and opportunities for magnetic design, e.g. use of new magnetic material or innovative manufacturing process. This paper is presenting the manufacturing process and characterisation of a composite material applied to the design of a magnetic components which is fully compliant with the printed circuit board (PCB) process. This paper is presenting results of the charac-terisation on the ferrite powder and on the soft magnetic compound (SMC), some insight are given on the material manufacturing before presenting additional characterisation procedures, especially for core losses measurements.

Guillaume Regnat

Papers

Optimized Power Modules for Silicon Carbide mosfet

Silicon carbide power chip on chip module based on embedded die technology with paralleled dies

Optimized power modules for silicon carbide MOSFET

Packaging 3D pour MOSFET en carbure de silicium

Characterisation of a Ferrite-Polymer Based Magnetic Material