Silicon carbide power chip on chip module based on embedded die technology with paralleled dies

TLDR: A parallelization technique enabling impedance balancing is developed for the layout and validated using four parallel Silicon Carbide (SiC) MOSFETs and the thermal management of the module is studied and die attach with direct copper filled vias is validated.

Abstract: A new three dimensional package based on Printed Circuit Board (PCB) embedded die technology is presented in this paper. The package takes advantage of the Power Chip On Chip (PCOC) concept, where commutation cell is housed within the bus bar, allowing a very low inductance design for the package of up to 0.25 nH. Two key design challenges with the package relate to the layout and the thermal management. Thus, a parallelization technique enabling impedance balancing is developed for the layout and validated using four parallel Silicon Carbide (SiC) MOSFETs. Gate circuit is carefully designed allowing low inductive behavior and low electromagnetic coupling. Finally, the thermal management of the module is studied and die attach with direct copper filled vias is validated.