In this paper, we propose a novel sorting algorithm that sorts input data integer elements on-the-fly without any comparison operations between the data—comparison-free sorting. We present a complete hardware structure, associated timing diagrams, and a formal mathematical proof, which show an overall sorting time, in terms of clock cycles, that is linearly proportional to the number of inputs, giving a speed complexity on the order of O(N). Our hardware-based sorting algorithm precludes the need for SRAM-based memory or complex circuitry, such as pipelining structures, but rather uses simple registers to hold the binary elements and the elements’ associated number of occurrences in the input set, and uses matrix-mapping operations to perform the sorting process. Thus, the total transistor count complexity is on the order of O(N). We evaluate an application-specified integrated circuit design of our sorting algorithm for a sample sorting of N = 1024 elements of size K = 10-bit using 90-nm Taiwan Semiconductor Manufacturing Company (TSMC) technology with a 1 V power supply. Results verify that our sorting requires approximately 4– $6~\mu \text{s}$ to sort the 1024 elements with a clock cycle time of 0.5 GHz, consumes 1.6 mW of power, and has a total transistor count of less than 750 000.

An Efficient O( $N$ ) Comparison-Free Sorting Algorithm

In this paper, we propose a new iterative process of sorting an array of signals, which differs from the known structures of sorting signals by uniformity, versatility, which allows direct and inverse sorting of an array of analog or digital signals. The basic elements of the proposed sorting structures are simple relational nodes for analogue signals from sensor devices and cameras. Such elements can be implemented on a different element basis, including, on devices for selecting a maximum or minimum of two analog or digital signals, which are implemented, in one of the variants, on CMOS current mirrors and carry out the function of continuous logic limited difference. We offer optoelectronic implementation of such basic relational element and a homogeneous sorting structure on such elements, consisting of two layers and a multichannel sampling and holding device. Nine signals corresponding to a selection window of a matrix sensor are fed to this structure, we sort them in five iterative steps, and at the output we receive the signals sorted by the rank, which, using the code controlled programmable multiplexer, generates an output signal, corresponding to the selected rank. We evaluate the technical parameters of such a relational preprocessor for nonlinear signal processing in image processors, sorting networks, multichannel parallel type sensor, processing, and encoding systems. The base cells consist of no more than 20 CMOS 1.5μm transistors, the total power consumption of the sorting node on 10 continuously logical base cells (CL BC) is 2mW, the supply voltage is 1.8÷3.3V, the range of an input photocurrent is 0.1÷24μA, the conversion cycle is 10μs, but can be improved by selecting other transistors and some modifications of the circuits. Such mixed analog processor is modeled in PSpice OrCad. The paper considers results of design and modeling of CL BC based on photosensitive cells with an extended electronic circuit and current mirrors (CM) with functions of preliminary subsequent analogue processing for creating picture type image processors (IP) with matrix parallel inputs-outputs. Such BCs and sorting nodes based on them have a number of advantages: high speed and reliability, simplicity, small power consumption, high integration level. We consider CL BC for methods of selection and rank preprocessing. In contrast to our previous works here we will dwell more on analogue preprocessing schemes for signals of neighboring cells. Let us show how the introduction of iterative sorting nodes extends the range of functions performed by the IPs. Examples of image processing with proposed preprocessor are simulated in MathCad and show the field of application of such coprocessors and new prospects for realization of linear and matrix photo-electronic structures with matrix operands. The essential difference is that the structure is iterative and allows to significantly reducing hardware costs in comparison with other hardware implementations of sorting networks. We discuss some aspects of possible rules and principles of learning and programmable configuration for the required function, relational work, and the implementation of hardware blocks for modifying such processors.

Design and simulation of image nonlinear processing relational preprocessor based on iterational sorting node

In this paper we proposed a new iterative process of sorting an array of signals, which differs from the known structures of sorting signals by uniformity, versatility, which allows direct and inverse sorting of an array of analog or digital signals. We proposed the structure of the processor based on the node that sorts the array of processed signals. Let us show the variety of the sorting node, which can be executed both iterative and pipeline–type, implementation of homogeneous sorting structure, consisting of two layers of base cells and a multichannel sampling and holding device and show that for a large number of operations and functions performed on image processing and filtering, it is necessary to sort by the signal level in the selected image window. The base cells consist of no more than 20 CMOS 1.5μm transistors, the total power consumption of the sorting node on 10 continuously logical base cells (CL BC) is 2mW, the supply voltage is 1.8÷3.3V, the range of an input photocurrent is 0.1÷24μA, the conversion cycle is 10μs. The paper considers results of design and modeling of CL BC based on current mirrors (CM) for creating picture type image processors (IP) with matrix parallel inputs-outputs. Such sorting nodes based on them have a number of advantages: high speed and reliability, simplicity, small power consumption, high integration level. The inclusion of an iterative node for sorting signals into a modified nonlinear IP structure makes it possible to significantly simplify its design and increase the functional capabilities of such processor. We evaluated the technical parameters of such a relational preprocessor. The simulation results confirm the proposed approaches to the design of sorting nodes of analog signals of the iterative type, which simplify the complexity of the nodes by an order of magnitude, ensuring their uniformity, regularity and simplicity of scaling. The power consumption of the processors does not exceed 2mW, the response and processing times are 10μs and can be less by an order of magnitude, the supply voltage is 1.8÷3.3V, and the operating currents are optimally in the range of 10÷20μA. The energy efficiency of the proposed preprocessor with the iterative sorting node is 25x109 op / s • W, which corresponds to the best technical solutions. In the work we are shown, that after sorting or comparative analysis of signals by levels of selected window of image, a promising opportunity appears to implement image processors with enhanced functionality using the new method of weighting-selecting rank differences of signals. The essence of the method is that by composing the differences of the signals ordered by rank and the upper level of their range, we can simultaneously form several resulting output signals, choosing the necessary difference signals from their set according to the control commands and weighing them additionally before the summation. We are shown that using this approach and the method of processing the current window signals significantly expands the set of operations and functions for filtering images, simplifying hardware implementation of IP, especially for analog and mixed technologies. We determined the set of executed command functions by such a processor based on the sorting node, show how it can be used to separate the rank from the array of signals and analyze the new approach for the programmable selection of the required rank or the difference between the signal ranks. The use of difference-rank decomposition allows to significantly expanding the transformations range, performed over the signals of the current fragment of the processed image. We determined set of basic possible executable instruction-functions by processors based on such a proposed method, presenting the simulation results in Mathcad, PSpice OrCad and other environments. We discussed the comparative evaluation of various modifications and options for implementing processor. We analyzed the new approach for the programmable choice of its function or set of functions, including the choice of the required differences between the ranks of signals and their weights. We show the results of design and modeling the proposed new FPGA-implementations of MIP. Simulation results show that processing time in such circuits does not exceed 25 nanoseconds. Circuits are simple, have low supply voltage (2.5 V), low power consumption (50mW), digital accuracy. Calculations show that when using an Altera FPGA chip EP3C16F484 Cyclone III family, it is possible to implement MIP with register memory for image size of 64*64 and window 3*3 in the one chip. For the chip for 2.5V and clock frequency 200MHz the power consumption will be at the level of 200mW, and the calculation time for pixel of filters will be at the level of 25ns.

Modeling nonlinear image processing algorithms using a processor based on the sorting node

A new iterative process for sorting array of signals, which differs from the known structures by uniformity and versatility, and allows direct and inverse sorting of analog or digital signal arrays was proposed in this paper. Simple relational nodes are basic elements of the proposed sorting structures. Such elements can be implemented on a different element basis, for example, on devices of selecting a maximum or minimum of two analog or digital signals, which can be implemented on CMOS current mirrors and carry out the continuous logic limited difference function. The homogeneous sorting structure on such elements implementation, consisting of two layers and a multichannel sampling and holding device was offered. Nine signals corresponding to a selection window of a matrix sensor are fed to this structure, and are sorted by five iterative steps, and at the output we receive the signals sorted by the rank, which, using the code controlled programmable multiplexer, generates an output signal, that corresponds to the selected rank. Technical parameters of such relational preprocessor were evaluated. The paper considers results of design and modeling of CL BC based on current mirrors (CM) for creating picture type image processors (IP) with matrix parallel inputsoutputs. Such sorting nodes have a number of advantages: high speed and reliability, simplicity, small power consumption, high integration level. The inclusion of an iterative node for sorting signals into a modified nonlinear IP structure makes possible to significantly simplify its design and increase the functional capabilities of such processor. The simulation results confirm the proposed approaches to the design of sorting nodes of analog signals of the iterative type. The power consumption of the processors does not exceed 2mW, the response and processing times are 10μs and can be less by an order of magnitude, the supply voltage is 1.8÷3.3V, and the operating currents are optimally in the range of 10÷20μA. The energy efficiency of the proposed preprocessor with the iterative sorting node is 25x109 operations per second per watt, which corresponds to the best technical solutions. In the work we show, that after sorting or comparative analysis of signals by levels, a promising opportunity appears to implement image processors with enhanced functionality using the new method of weighting-selecting rank differences of signals. The essence of the method is that by composing the differences of the signals ordered by rank and the upper level of their range, we can simultaneously form several resulting output signals, choosing the necessary difference signals from their set according to the control commands and weighing them additionally before the summation. We show that using this approach and the method of processing we can significantly expands the set of operations and functions for image filtering, simplifying hardware implementation of IP, especially for analog and mixed technologies. We determined set of basic executable instruction-functions of the processors, presenting the simulation results in Mathcad, PSpice OrCad and other environments. We discussed the comparative evaluation of various modifications and options for implementing processor. We analyzed the new approach for the programmable selecting function or set of functions, including the selecting the required differences between the ranks of signals and their weights. We show the results of design and modeling the proposed new FPGA-implementations of MIP. Simulation results show that processing time in such circuits does not exceed 25 nanoseconds. Circuits are simple, have low supply voltage (2.5 V), low power consumption (50mW), digital accuracy. Calculations show that in the case of using an Altera FPGA chip EP3C16F484 Cyclone III family, it is possible to implement MIP with register memory for image size of 64*64 and window 3*3 in the one chip. For the chip for 2.5V and clock frequency 200MHz the power consumption will be at the level of 200mW, and the calculation time for pixel of filters will be at the level of 25ns.

Multifunctional image processor based on rank differences signals weighing-selection processing method and their simulation

A high-speed real-time currency sorting system based on SOPC of FPGA is designed against the existing problems in our country, such as the high complexity, the lower stability, the low real-time performance of complex algorithms for high-speed digital image signal and that the system is difficult to upgrade in real time, etc. The methods of software simulation, real-time debugging online are applied; the real-time processing of complex image algorithms has been achieved successfully and the system complexity has been reduced; the integration and stability of the system have been greatly improved. Furthermore the operation of FPGA could be performed in parallel and the responsive time of its hardware could be accurate to nanosecond (ns) level. So the real-time processing properties of the system have more advantages against other processing platforms. Because of the system programmable performance, the real-time updates of the system without changing the hardware circuit have also been implemented.

Guo Tao

Papers

High-speed FPGA-based SOPC application for currency sorting system