Proceedings ArticleDOI
High-speed FPGA-based SOPC application for currency sorting system
Wu Jianping,Yutang Ye,Liu Lin,Huang Bingquan,Guo Tao +4 more
- Vol. 2, pp 85-89
Reads0
Chats0
TLDR
The real-time processing of complex image algorithms has been achieved successfully and the system complexity has been reduced, and the integration and stability of the system have been greatly improved.Abstract:
A high-speed real-time currency sorting system based on SOPC of FPGA is designed against the existing problems in our country, such as the high complexity, the lower stability, the low real-time performance of complex algorithms for high-speed digital image signal and that the system is difficult to upgrade in real time, etc. The methods of software simulation, real-time debugging online are applied; the real-time processing of complex image algorithms has been achieved successfully and the system complexity has been reduced; the integration and stability of the system have been greatly improved. Furthermore the operation of FPGA could be performed in parallel and the responsive time of its hardware could be accurate to nanosecond (ns) level. So the real-time processing properties of the system have more advantages against other processing platforms. Because of the system programmable performance, the real-time updates of the system without changing the hardware circuit have also been implemented.read more
Citations
More filters
Journal ArticleDOI
An Efficient O( $N$ ) Comparison-Free Sorting Algorithm
TL;DR: A novel sorting algorithm that sorts input data integer elements on-the-fly without any comparison operations between the data—comparison-free sorting is proposed.
Proceedings ArticleDOI
Design and simulation of image nonlinear processing relational preprocessor based on iterational sorting node
TL;DR: A new iterative process of sorting an array of signals, which differs from the known structures of sorting signals by uniformity, versatility, which allows direct and inverse sorting of anarray of analog or digital signals is proposed.
Proceedings ArticleDOI
Modeling nonlinear image processing algorithms using a processor based on the sorting node
TL;DR: In this article, the authors proposed a new iterative process of sorting an array of signals, which differs from the known structures of sorting signals by uniformity, versatility, and ability to perform direct and inverse sorting.
Proceedings ArticleDOI
Multifunctional image processor based on rank differences signals weighing-selection processing method and their simulation
TL;DR: After sorting or comparative analysis of signals by levels, a promising opportunity appears to implement image processors with enhanced functionality using the new method of weighting-selecting rank differences of signals.
References
More filters
Journal ArticleDOI
System-on-a-programmable-chip development platforms in the classroom
Tyson S. Hall,James O. Hamblen +1 more
TL;DR: This paper describes the authors' experiences using a system-on-a-programmable-chip (SOPC) approach to support the development of design projects for upper-level undergraduate students in their electrical and computer engineering curriculum.
Proceedings ArticleDOI
Using an FPGA Processor Core and Embedded Linux for Senior Design Projects
Tyson S. Hall,James O. Hamblen +1 more
TL;DR: This paper describes the experiences using a low-cost SoPC FPGA board and an open source RTOS for senior design projects and developed a custom Nios processor design and customized a muClinux OS to support theirSenior design projects.
Proceedings ArticleDOI
FPGA-based embedded system design
TL;DR: The general introduction of embedded system and the FPGA-based SOPC development are discussed and a data transmitting/receiving converter between serial port and network interface is taken as a design example.
Proceedings ArticleDOI
A host co-processor FPGA-based Architecture for Fast Image Processing
John Kalomiros,John N. Lygouras +1 more
TL;DR: A general system architecture for fast image processing, based on a field programmable gate array (FPGA) co-processor and a host computer, is presented and evaluated and a range of applications is discussed.