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Design Of Analog Cmos Integrated Circuits

We propose an adaptive ramp control strategy with self-tuning offset and amplitude, as a simple yet effective solution for controlling dc–dc power converters despite load and input voltage variations. It is shown that our control technique is able to suppress chaos and subharmonic oscillations for a wide range of input voltage and loads. Furthermore, a systematic methodology based on bifurcation diagrams for tuning the controller is proposed. Stability and performance analysis have been done together with a proper comparison of our technique, and the classical control strategies often used in the literature. Particularly, $V_{\text{\rm in}}$ feed-forward and adaptive slope compensation controllers have been considered for the buck and boost converters, respectively. Finally, the effectiveness of the control technique is validated for the buck converter via experimental setup.

Adaptive Ramp Technique for Controlling Chaos and Subharmonic Oscillations in DC–DC Power Converters

In this paper, a radiation-tolerant phase-locked loop (PLL) is designed and fabricated with 130 nm PD-SOI technology. A current-based charge pump is hardened using a current compensation technique in combination with the differential charge cancellation (DCC) layout of the complementary switches. Besides, the stacked SOI transistors are employed to mitigate single-event effects of the voltage-controlled oscillator. The experimental results show that the proposed PLL has no significant jitter variations under heavy-ion experiments, compared with TMR-hardened PLL. Besides, pulsed-laser testing comprehensively characterizes the single-event transients of the PLL and demonstrates its radiation tolerant performance.

Single-Event Transient Characterization of a Radiation-Tolerant Charge-Pump Phase-Locked Loop Fabricated in 130 nm PD-SOI Technology

We demonstrate a fully integrated linear regulator for multisupply voltage microprocessors implemented in a 90 nm CMOS technology. Ultra-fast single-stage load regulation achieves a 0.54-ns response time at 94% current efficiency. For a 1.2-V input voltage and 0.9-V output voltage the regulator enables a 90 mVp-p output droop for a 100-mA load step with only a small on-chip decoupling capacitor of 0.6 nF. By using a PMOS pull-up transistor in the output stage we achieved a small regulator area of 0.008 mm 2 and a minimum dropout voltage of 0.2 V for 100 mA of output current. The area for the 0.6-nF MOS capacitor is 0.090 mm 2 .

Area-efficient linear regulator with ultra-fast load regulation

An ultra-low power output-capacitorless low-dropout (LDO) regulator with a slew-rate-enhanced (SRE) circuit is introduced. The increased slew rate is achieved by sensing the transient output voltage of the LDO and then charging (or discharging) the gate capacitor quickly. In addition, a buffer with ultra-low output impedance is presented to improve line and load regulations. This design is fabricated by SMIC 0.18 μm CMOS technology. Experimental results show that, the proposed LDO regulator only consumes an ultra-low quiescent current of 1.2 μA. The output current range is from 10 μA to 200 mA and the corresponding variation of output voltage is less than 40 mV. Moreover, the measured line regulation and load regulation are 15.38 mV/V and 0.4 mV/mA respectively.

https://iopscience.iop.org/article/10.1088/1674-4926/39/3/035002/pdf

An ultra-low power output capacitor-less low-dropout regulator with slew-rate-enhanced circuit

A radiation-hardened-by-design phase-locked loop (PLL) with a frequency range of 200 to 1000 MHz is proposed. By presenting a novel charge compensation circuit, composed by a lock detector circuit, two operational amplifiers, and four MOS devices, the proposed PLL significantly reduces the recovery time after the presence of a single event transient (SET). Comparing with many traditional hardened methods, most of which endeavor to enhance the immunity of the charge pump output node to an SET, the novel PLL can also decrease its susceptibility in the presence of an SET in other blocks. A novel system model is presented to describe immunity of a PLL to an SET and used to compare the sensitivity of traditional and hardened PLLs to an SET. An SET is simulated on Sentaurus TCAD simulation workbench to model the induced pulse current. Post simulation with a 130 nm CMOS process model shows that the recovery time of the proposed PLL reduces by up to 93.5% compared with the traditional one, at the same time, the charge compensation circuit adds no complexity to the systemic parameter design.

A single-event-hardened phase-locked loop using the radiation-hardened-by-design technique

To improve the compensation for the inherent instability in a current mode converter, the adaptive slope compensation, giving attention to the problems of the traditional compensation on compensation accuracy, loading capability and turning jitter, is presented. Based on the analysis of current loop, by detecting the input and output voltage, converting the adaptive slope compensation current, the compensation of the current loop is optimized successfully. It can not only improve the compensation accuracy but also eliminate the over compensation, the turning jitter and the poor loading capability in the reported slope compensation. A power supply chip with adaptive slope compensation has been fabricated in a 0.35 μm CMOS process. The measurement results show that the chip starts up and operates steadily with the constant current limit under conditions of 5 V input voltage, from 10% to 100% duty cycle.

https://iopscience.iop.org/article/10.1088/1674-4926/31/12/125004/pdf

Design and implementation of adaptive slope compensation in current mode DC?DC converter

To achieve a constant current limit, low power consumption and high driving capability, a micro-power LDO with a piecewise voltage-foldback current-limit circuit is presented. The current-limit threshold is dynamically adjusted to achieve a maximum driving capability and lower quiescent current of only 300 nA. To increase the loop stability of the proposed LDO, a high impedance transconductance buffer under a micro quiescent current is designed for splitting the pole that exists at the gate of the pass transistor to the dominant pole, and a zero is designed for the purpose of the second pole phase compensation. The proposed LDO is fabricated in a BiCMOS process. The measurement results show that the short-circuit current of the LDO is 190 mA, the constant limit current under a high drop-out voltage is 440 mA, and the maximum load current under a low drop-out voltage is up to 800 mA. In addition, the quiescent current of the LDO is only 7 μA, the load regulation is about 0.56% on full scale, the line regulation is about 0.012%/V, the PSRR at 120 Hz is 58 dB and the drop-out voltage is only 70 mV when the load current is 250 mA.

A micro-power LDO with piecewise voltage foldback current limit protection

To improve the power sequencing performance of the system-on-a-chip (SOC), a novel embedded soft-start circuit is presented. A seamless soft-start reference voltage is obtained with 7 bits DAC, which can not only restrain the turning point overshoot, but also improve the output accuracy and the poor loading capability, reduce the pin number and save PCB area. The whole DC–DC converter has been fabricated in a 0.35 μm CMOS process. The measurement results show that the chip starts up successfully with 250 μs soft-start time under conditions of 400 kHz switching frequency, 2.5 V DC–DC output and 1.8 V LDO output. Stable operation after soft-start is also shown.

http://iopscience.iop.org/article/10.1088/1674-4926/31/5/055012/pdf

A novel embedded soft-start circuit for SOC power supply

A Three-level chopping technique to reduce offset caused by mismatch of the Wilson Current-mirror and PNP bipolar transistor is descried and presented. Input referred offset voltage of the PNP transistor is reduced on first level. On second level, Wilson Current-mirror offset is further reduced along with the low frequency 1/f noise caused by the self-biased circuit. The last level is used to reduce offset of self-biased circuit two. The proposed BGR was simulated in a temperature range from -45°C and 125°C. Simulate results showed that the standard deviation of the BGR output voltage without chopping is 9 times higher than that of when chopping is enabled. The proposed three-level chopping technique is verified improving performance characteristics of conventional BGR circuit. The maximum supply current is 36uA and the area of layout is 0. 085mm2 with a standard 0. 13um 1P4M CMOS process.

Guo Zhongjie

Papers

A single-event-hardened phase-locked loop using the radiation-hardened-by-design technique

Design and implementation of adaptive slope compensation in current mode DC?DC converter

A micro-power LDO with piecewise voltage foldback current limit protection

A novel embedded soft-start circuit for SOC power supply

High-Precision Bandgap Voltage Generation Method With Chopper Stabilization Technique