Recently, transistor scaling is approaching its physical limit, hindering the further development of the computing capability. In the post-Moore era, emerging logic and storage devices have been the fundamental hardware for expanding the capability of intelligent computing. In this article, the recent progress of ferroelectric devices for intelligent computing is reviewed. The material properties and electrical characteristics of ferroelectric devices are elucidated, followed by a discussion of novel ferroelectric materials and devices that can be used for intelligent computing. Ferroelectric capacitors, transistors, and tunneling junction devices used for low-power logic, high-performance memory, and neuromorphic applications are comprehensively reviewed and compared. In addition, to provide useful guidance for developing high-performance ferroelectric-based intelligent computing systems, the key challenges for realizing ultrascaled ferroelectric devices for high-efficiency computing are discussed.

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Ferroelectric Devices for Intelligent Computing

Magnetic skyrmion technology is promising for the next-generation spintronics-based memory and neuromorphic computing due to their small size, non-volatility and low depinning current density. However, the Magnus force originating from the skyrmion Hall effect causes the skyrmion to move along a curved trajectory, which may lead to the annihilation of the skyrmion in a nanotrack during current-induced skyrmion motion. Consequently, circuits utilizing skyrmionic motion need to be designed to limit the impact of the skyrmion Hall effect. In this work, we propose a design of an artificial neuron, and a synapse using the bilayer device consisting of two antiferromagnetically exchange coupled ferromagnetic layers, which achieves robustness against the skyrmion Hall effect by nullifying the Magnus force. Using micromagnetic simulations, we show that the bilayer device can work as an artificial neuron and also as a synapse by modifying its uniaxial anisotropy. We also demonstrate that our proposed skyrmionic synapse has an intrinsic property of perfectly linear and symmetric weight update, which is highly desirable for the synapse operation. A spiking neural network implemented using our proposed synapse and neuron was simulated and showed to achieve 96.23\% accuracy in performing classification on the MNIST handwritten digit dataset.

Bilayer-Skyrmion-Based Design of Neuron and Synapse for Spiking Neural Network

With the rapid growth of the semiconductor manufacturing industry, it has been evident that device simulation has been considered a sluggish process. Therefore, due to downscaling of semiconductor devices, it is significantly expensive to obtain the inevitable device simulation data because it requires complex analysis of various factors. To develop a competent technique to analyze the performance of the line tunnel field-effect transistors (TFETs), the 3-D stochastic device simulation is integrated with a machine learning (ML) algorithm, named random forest regressor (RFR). Despite producing tremendous researches by the RFR model in the field of computer vision, the adoption of these ML algorithms in the field of the semiconductor industry has a lot of margin for progress. The ML-based RFR model is exploited to predict the effect of variability sources of line TFET under different biasing conditions. Results are promising and reducing the computational cost of device simulation by 99%. The prediction of effect of source variation is less than 1% as compared to the device simulation of line TFET. The application of the RFR on the line TFET device exhibits the power and flexibility of this approach because its evaluation with different bias conditions shows outstanding results. 

Device-Simulation-Based Machine Learning Technique for the Characteristic of Line Tunnel Field-Effect Transistors

Data intensive applications such as AI (Artificial Intelligence) and IoT (Internet of Things) demand high performance and highly reliable non-volatile memories (NVM). FeFET offers several exciting features such as faster write/read speed, high density, low power, non-destructive readout, random access and high endurance compared with existing mainstream flash memories. Large memory window (MW) and robust device reliability in terms of endurance and retention time are the key requirements for FeFETs in practical NVM applications. Ferroelectric materials, channel materials, gate electrode materials and seed layers can significantly affect the memory performance of FeFETs. Therefore, this article critically reviews the memory performance FeFETs over the last 50 years, various FeFET architectures, the role of 2D-materials in FeFETs, emergence of organic materials for the development of organic FeFETs, role of oxides as channel materials, advancements in fabrication process and reliability concerns and emerging applications of FeFETs. 

Ferroelectric Field Effect Transistors (FeFETs):Advancements, Challenges and Exciting Prospects for Next Generation Non-Volatile Memory (NVM) Applications

A full understanding of the impact of charge trapping on the memory window (MW) of HfO2-based ferroelectric field effect transistors (FeFETs) will permit the design of program and erase protocols, which will guide the application of these devices and maximize their useful life. The effects of charge trapping have been studied by changing the parameters of the applied program and erase pulses in a test sequence. With increasing the pulse amplitude and pulse width, the MW increases first and then decreases, a result attributed to the competition between charge trapping (CT) and ferroelectric switching (FS). This interaction between CT and FS is analyzed in detail using a single-pulse technique. In addition, the experimental data show that the conductance modulation characteristics are affected by the CT in the analog synaptic behavior of the FeFET. Finally, a theoretical investigation is performed in Sentaurus TCAD, providing a plausible explanation of the CT effect on the memory characteristics of the FeFET. This work is helpful to the study of the endurance fatigue process caused by the CT effect and to optimizing the analog synaptic behavior of the FeFET.

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Effects of Charge Trapping on Memory Characteristics for HfO2-Based Ferroelectric Field Effect Transistors

In this article, an analog synapse based on a nonvolatile field-effect transistor with amorphous ZrO2 dielectrics has been fabricated and demonstrated. The conductance modulation properties of the devices have been systematically evaluated. Due to the polarization switching dynamics of the ferroelectric-like amorphous ZrO2 dielectric, which is attributable to the voltage-driven oxygen vacancies and negative charges dipoles, the proposed ZrO2-based devices exhibit superior synaptic characteristics, including good symmetry and linearity for both potentiation and depression, with small cycle-to-cycle variations. The ratio of maximum conductance and minimum conductance ( ${G}_{max}/{G}_{min})$ of devices reaches 130, with conductance states over 30. Also, spike-timing-dependent plasticity (STDP) has been mimicked in the devices successfully. Furthermore, based on the experimental STDP characteristics and conductance modulation properties of potentiation and depression, a spiking neural network architecture constructed by the proposed ZrO2-based synapses has been simulated. High offline and online learning accuracy of 94% and 87%, respectively, on the handwritten digits dataset, has been achieved.

Analog Synapses Based on Nonvolatile FETs With Amorphous ZrO2 Dielectric for Spiking Neural Network Applications

Optimization and Performance Prediction of Tunnel Field-Effect Transistors Based on Deep Learning

Convolutional neural network algorithm has been widely used in unmanned 3D perception and object detection, and FPGA has been more widely used in implementing convolutional neural network with its ultra-low power and ultra-high performance. In this paper, the heterogeneous computing method based on FPGA and various optimization methods are adopted to design the heterogeneous computing structure that meets the performance requirements of the unmanned vehicle algorithm, as well as the specific methods and optimization strategies for heterogeneous implementation. The results show that by adopting the method of heterogeneous optimization design, compared with the CPU calculation method, both the power consumption and the speed have been greatly improved, meeting the requirements of the data processing speed of the unmanned vehicle.

Research of Heterogeneous Acceleration Optimization of Convolutional Neural Network Algorithm for Unmanned Vehicle Based on FPGA

The data throughput in the von Neumann architecture-based computing system is limited by its separated processing and memory structure, and the mismatching speed between the two units. As a result, it is quite difficult to improve the energy efficiency in conventional computing system, especially for dealing with unstructured data. Meanwhile, artificial intelligence and robotics nowadays still behave poorly in autonomy, creativity, and sociality, which has been considered as the unimaginable computational requirement for sensorimotor skills. These two plights have urged the imitation and replication of the biological systems in terms of computing, sensing, and even motoring. Hence, the so-called neuromorphic system has drawn worldwide attention in recent decade, which is aimed at addressing the aforementioned needs from the mimicking of neural system. The recent developments on emerging memory devices, nanotechnologies, and materials science have provided an unprecedented opportunity for this aim.

2022 roadmap on neuromorphic devices and applications research in China

Nanoantenna fusion photonics and nanotechnology can manipulate light through the ultra-thin structure composed of sub-wavelength antennas, and meet the important requirements for miniaturized optical components, completely changing the field of optics. However, the device design process is still time-consuming and consumes computing resources. Besides, the professional knowledge requirements of engineers are also high. Relying on the algorithm’s inference ability and excellent computing ability, artificial intelligence has great potential in the fields of material design, material screening, and device performance prediction. However, the deep learning (DL) requires a mass of data. Therefore, this article proposes a method for the forward and inverse design of nanoantenna based on DL. Compared with the previous work, the network uses a two-dimensional matrix as input, which has a simple structure and is more suitable for the advantages of deep netural network. Simultaneously, the small datasets can be used to achieve higher accuracy. In the forward prediction, 100% of the data error is less than 0.007; in the inverse prediction, the data with error less than 0.05 accounted for 90%, 99.8% and 100% of the length, height, and width’s datasets. It demonstrates that the method can improve the automation of the design process and reduce the consumption of computer resources.

Guosheng Wang

Papers

Analog Synapses Based on Nonvolatile FETs With Amorphous ZrO2 Dielectric for Spiking Neural Network Applications

Optimization and Performance Prediction of Tunnel Field-Effect Transistors Based on Deep Learning

Research of Heterogeneous Acceleration Optimization of Convolutional Neural Network Algorithm for Unmanned Vehicle Based on FPGA

2022 roadmap on neuromorphic devices and applications research in China

The accelerated design of the nanoantenna arrays by deep learning