An improved conductivity vertical channel semiconductor device includes an insulated gate electrode disposed adjacent a substantial portion of the voltage supporting region. In response to an appropriate bias, the control electrode couples to the electric field originating on charges within the voltage supporting region to reorient the electric field associated with those charges toward the gate electrode and transverse to the direction of current flow through the device. Improved control of the electric field within the voltage supporting region allows the doping concentration, and hence the conductivity of the channel, to be improved without a concomitant decrease in breakdown voltage. Accordingly, the channel width and cell repeat distance of the improved device can be reduced, allowing for an improved current density to be established throughout an overall device cell structure. The charge control region of the voltage supporting layer exhibits an aspect ratio of 0.5.

Semiconductor devices exhibiting minimum on-resistance

A high frequency field effect transistor of gallium arsenide or other III-V semiconductor compounds has a preferentially etched trapezoidal groove structure in the top surface which creates parallel trapezoidal semiconductor fingers that are wider at the top than at the bottom. Schottky gates or junction gates are fabricated within the grooves surrounding the elongated fingers. The vertical conducting channels between the gates are narrow leading to a high blocking gain, and more contact area is available at the top of the device.

Vertical field effect transistor with improved gate and channel structure

A high power high frequency field effect transistor is achieved with a vertical structure of gallium arsenide including a semi-insulating substrate, a conductive layer over the substrate, a narrow-central post having small metal gate electrodes on each side, metal drain electrodes on the conductive layer spaced from the central post and a metal source electrode supported on the central post. A deep channel around the post separates the metal drains, gates and source. Increased power is obtained from a cellular unit including two parallel source stripes, four gates and three drains. The drains are connected together by the conductive layer and a drain pad at one end, and the gates are connected at the other end by a gate pad on an outer region of the substrate. The gate connections to the pad are isolated from the conductive layer by a bridge over a space etched in the lower layer. A method for fabrication of this structure is also provided.

Vertical MESFET with air spaced gate electrode

A process for substantially reducing the overlap between a gate and the source and drain regions of a field-effect transistor is disclosed. Lateral etching of a polysilicon gate provides overhangs which extend from a gate masking member. Source/drain regions are formed by ion implanting through the gate oxide layer. A small amount of dopant is implanted through the overhangs providing a low concentration of dopant in alignment with the gate. During subsequent processing, this low concentration of dopant does not substantially diffuse as do regions of higher concentration. Significant reduction in Miller capacitance is obtained along with improved punch-through characteristics.

Shadow masking process for forming source and drain regions for field-effect transistors and like regions

An MOS transistor is fabricated which is especially suitable for use in the VHF and UHF regions, comprising a common source lateral MOSFET formed on a substrate, the substrate serving as the connection for the source to the header. The substrate, which is preferably P-type, has P-type and N-type epitaxial regions lying thereon and a sinker which forms a connection from source to substrate. The vertically isolated field effect transistor has a drain on top of a mesa on the N-type epitaxial region of the substrate, a gate in the contact region overhanging the edge of a channel formed adjacent to the mesa, and a source in the lateral edges of the groove defining the edge of the mesa. The process provides for simultaneous diffusion of the source and drain regions, followed by a metal masking step for connection of the diffused source which lies in the lateral edge of the groove to the sinker, effectively connecting the source to the substrate.

Method of fabrication lateral FET structure having a substrate to source contact

There is disclosed a method of making a metal-oxide silicon field-effect transistor (MOSFET) capable of delivering substantial power (5 to 10 watts) in the microwave frequency range (about 5 Gigahertz) and operating as an amplifier over a wide bandwidth through a reasonably high input impedance exceeding about 5 ohms. The method is practiced with a layered blank of silicon having, say, an N+ substrate on which is a Player; there is a second N+ layer on the P-layer. Regions, each having a surface for deposit of a drain, are prepared on the second layer. Grooves are etched undercutting these regions so that they overhang the grooves. The gate and drain electrodes are deposited simultaneously by linear beams of vapor at supplementary angles to the prepared surfaces. The angles and the length of the overhangs are such that the gate electrodes extend only along the projections of the edges of the contiguous Players which extend along the groove, minimizing the capacitance between the gate electrode and the other electrodes. There is also disclosed a MOSFET produced in the practice of this invention.

Gutknecht Peter

Papers

Solid state components