Patent
Solid state components
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TLDR
In this paper, a method of making a metal-oxide silicon field effect transistor (MOSFET) capable of delivering substantial power (5 to 10 watts) in the microwave frequency range (about 5 Gigahertz) and operating as an amplifier over a wide bandwidth through a reasonably high input impedance exceeding about 5 ohms.Abstract:
There is disclosed a method of making a metal-oxide silicon field-effect transistor (MOSFET) capable of delivering substantial power (5 to 10 watts) in the microwave frequency range (about 5 Gigahertz) and operating as an amplifier over a wide bandwidth through a reasonably high input impedance exceeding about 5 ohms. The method is practiced with a layered blank of silicon having, say, an N+ substrate on which is a Player; there is a second N+ layer on the P-layer. Regions, each having a surface for deposit of a drain, are prepared on the second layer. Grooves are etched undercutting these regions so that they overhang the grooves. The gate and drain electrodes are deposited simultaneously by linear beams of vapor at supplementary angles to the prepared surfaces. The angles and the length of the overhangs are such that the gate electrodes extend only along the projections of the edges of the contiguous Players which extend along the groove, minimizing the capacitance between the gate electrode and the other electrodes. There is also disclosed a MOSFET produced in the practice of this invention.read more
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Semiconductor devices exhibiting minimum on-resistance
TL;DR: In this article, an improved conductivity vertical channel semiconductor device includes an insulated gate electrode disposed adjacent a substantial portion of the voltage supporting region to reorient the electric field associated with those charges toward the gate electrode and transverse to the direction of current flow through the device.
Patent
Vertical field effect transistor with improved gate and channel structure
TL;DR: In this article, a high frequency field effect transistor of gallium arsenide or other III-V semiconductor compounds has a preferentially etched trapezoidal groove structure in the top surface which creates parallel trapezoid semiconductor fingers that are wider at the top than at the bottom.
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Vertical MESFET with air spaced gate electrode
Ho-Chung Huang,Ralph J. Matarese +1 more
TL;DR: In this paper, a high power high frequency field effect transistor is achieved with a vertical structure of gallium arsenide including a semi-insulating substrate, a conductive layer over the substrate, and a narrow central post having small metal gate electrodes on each side, metal drain electrodes on the conductive layers spaced from the central post and a metal source electrode supported on the central posts.
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Shadow masking process for forming source and drain regions for field-effect transistors and like regions
TL;DR: In this paper, a method for substantially reducing the overlap between a gate and the source and drain regions of a field effect transistor is described, where a small amount of dopant is implanted through the overhangs providing a low concentration of dopamine in alignment with the gate.
Patent
Method of fabrication lateral FET structure having a substrate to source contact
TL;DR: In this paper, an MOS transistor is fabricated which is especially suitable for use in the VHF and UHF regions, comprising a common source lateral MOSFET formed on a substrate, the substrate serving as the connection for the source to the header.
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Fabrication of semiconductor devices having low thermal inpedance bonds to heat sinks
TL;DR: In this article, a layer of contact metallization is applied over the surface of a semiconductor slice having a P-N junction, and a heat sink layer of high conductivity metal, such as copper, is applied with a sufficient thickness to provide a predetermined heat dissipation.
Patent
Methods for making transistor structures
TL;DR: In this paper, a high frequency field effect transistor is made by first epitaxially growing semiconductor channel and drain layers over a source layer, and an oxide layer is formed on the upper drain layer which acts as a mask during etching of the epitaxial layers.
Patent
Method of making a semiconductor device
Nakamura Keiichi,Kuroo Yoshiyasu +1 more
TL;DR: In this paper, a passivated PN junction semi-conductor device is manufactured by a method which includes depositing on the semiconductor surface a material (e.g. lead, lead oxide, magnesium, zirconium, aluminium or beryllium) to form a glass at a temperature lower than that at which the semiconductor itself would be oxidized.