An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

In this paper, recent progress of phase change memory (PCM) is reviewed. The electrical and thermal properties of phase change materials are surveyed with a focus on the scalability of the materials and their impact on device design. Innovations in the device structure, memory cell selector, and strategies for achieving multibit operation and 3-D, multilayer high-density memory arrays are described. The scaling properties of PCM are illustrated with recent experimental results using special device test structures and novel material synthesis. Factors affecting the reliability of PCM are discussed.

Phase Change Memory

Nonvolatile RAM using resistance contrast in phase-change materials [or phase-change RAM (PCRAM)] is a promising technology for future storage-class memory. However, such a technology can succeed only if it can scale smaller in size, given the increasingly tiny memory cells that are projected for future technology nodes (i.e., generations). We first discuss the critical aspects that may affect the scaling of PCRAM, including materials properties, power consumption during programming and read operations, thermal cross-talk between memory cells, and failure mechanisms. We then discuss experiments that directly address the scaling properties of the phase-change materials themselves, including studies of phase transitions in both nanoparticles and ultrathin films as a function of particle size and film thickness. This work in materials directly motivated the successful creation of a series of prototype PCRAM devices, which have been fabricated and tested at phase-change material cross-sections with extremely small dimensions as low as 3 nm × 20 nm. These device measurements provide a clear demonstration of the excellent scaling potential offered by this technology, and they are also consistent with the scaling behavior predicted by extensive device simulations. Finally, we discuss issues of device integration and cell design, manufacturability, and reliability.

Phase-change random access memory: a scalable technology

An electrosurgical system is disclosed. The electrosurgical system includes an electrosurgical generator adapted to supply electrosurgical energy to tissue. The electrosurgical generator includes impedance sensing circuitry which measures impedance of tissue, a microprocessor configured to determine whether a tissue reaction has occurred as a function of a minimum impedance value and a predetermined rise in impedance, wherein tissue reaction corresponds to a boiling point of tissue fluid, and an electrosurgical instrument including at least one active electrode adapted to apply electrosurgical energy to tissue.

Vessel sealing system

A phase-change memory element with side-wall contacts is disclosed, which has a bottom electrode. A non-metallic layer is formed on the electrode, exposing the periphery of the top surface of the electrode. A first electrical contact is on the non-metallic layer to connect the electrode. A dielectric layer is on and covering the first electrical contact. A second electrical contact is on the dielectric layer. An opening is to pass through the second electrical contact, the dielectric layer, and the first electrical contact and preferably separated from the electrode by the non-metallic layer. A phase-change material is to occupy one portion of the opening, wherein the first and second electrical contacts interface the phase-change material at the side-walls of the phase-change material. A second non-metallic layer may be formed on the second electrical contact. A top electrode contacts the top surface of the outstanding terminal of the second electrical contact.

Phase-change memory

An electrically erasable phase change memory utilizing a stoichiometrically balanced phase change material in which both the switching times and the switching energies required for the transitions between the amorphous and the crystalline states are substantially reduced below those attainable with prior art electrically erasable phase change memories. One embodiment of the invention comprises an integrated circuit implementation of the memory in a high bit density configuration in which manufacturing costs are correspondingly reduced and performance parameters are further improved.

Electrically erasable phase change memory

An apparatus including a contact on a substrate, a dielectric material overlying the contact, a phase change element overlying the dielectric material on a substrate, and a heater element disposed in the dielectric material and coupled to the contact and the phase change element, wherein a portion of the dielectric material comprises a thermal conductivity less than silicon dioxide. A method including introducing over a contact formed on a substrate, a dielectric material, a portion of which comprises a thermal conductivity less than silicon dioxide, introducing a heater element through the dielectric material to the contact, and introducing a phase change material over the dielectric material and the heater element.

Method to enhance performance of thermal resistor device

A method comprising forming a sacrificial layer over less than the entire portion of a contact area on a substrate, the sacrificial layer having a thickness defining an edge over the contact area, forming a spacer layer over the spacer, the spacer layer conforming to the shape of the first sacrificial layer such that the spacer layer comprises an edge portion over the contact area adjacent the first sacrificial layer edge, removing the sacrificial layer, while retaining the edge portion of the spacer layer over the contact area, forming a dielectric layer over the contact area, removing the edge portion, and forming a programmable material to the contact area formerly occupied by the edge portion. An apparatus comprising a volume of programmable material, a conductor, and an electrode disposed between the volume of programmable material and the conductor, the electrode having a contact area at one end coupled to the volume of programmable material, wherein the contact area is less than the surface area at the one end.

Reduced area intersection between electrode and programming element

A method including, in a dielectric material over a contact on a substrate, forming a trench to the contact; introducing an electrode material along the sidewalls of the trench; introducing a phase change material over material along a first sidewall; and modifying the electrode material along the sidewalls such that only the material along the first sidewall acts as a conductive path between the contact and the phase change material. An apparatus including a chalcogenide memory element; a contact; and a heater element comprising two leg portions, a first leg portion coupled to the contact and the chalcogenide memory element, and only the first leg portion acts as a conductive path between the contact and the chalcogenide memory element.

Reduced contact area of sidewall conductor

The present invention is a computational unit comprising a logic processing device (10), and a memory array (30) deposited on top of and communicating with the logic processing device. More specifically, the present invention is a computational unit comprising a logic processing device (10), and electrically erasable phase change memory (30) deposited on top of and communicating with the logic processing device.

Guy C. Wicker

Papers

Electrically erasable phase change memory

Method to enhance performance of thermal resistor device

Reduced area intersection between electrode and programming element

Reduced contact area of sidewall conductor

Second-layer phase change memory array on top of a logic device