A technique that combines the high-frequency behavior of a single-stage op amp with the high DC gain of a multistage design is presented. This technique is based on the concept that a very high DC gain can be achieved in combination with any unity-gain frequency achievable by a (folded-) cascode design. Bode-plot measurements for an op amp realized in a 1.6- mu m process show a DC gain of 90 dB and a unity-gain frequency of 116 MHz (16-pF load). Settling measurements with a feedback factor of 1/3 show a fast single-pole settling behavior corresponding to a closed-loop bandwidth of 18 MHz (35-pF load) and a settling accuracy better than 0.03%. This technique does not cause any loss in output voltage swing. At a supply voltage of 5.0 V an output swing of about 4.2 V is achieved without loss in DC gain. The above advantages are achieved with a 30% increase in chip area and a 15% increase in power consumption. >

A fast-settling CMOS op amp for SC circuits with 90-dB DC gain

A multistage operational transconductance amplifier with a feedforward compensation scheme which does not use Miller capacitors is introduced. The compensation scheme uses the positive phase shift of left-half-plane (LHP) zeroes caused by the feedforward path to cancel the negative phase shift of poles to achieve a good phase margin. A two-stage path increases further the low frequency gain while a feedforward single-stage amplifier makes the circuit faster. The amplifier bandwidth is not compromised by the absence of the traditional pole-splitting effect of Miller compensation, resulting in a high-gain wideband amplifier. The capacitors of a capacitive amplifier using the proposed techniques can be varied more than a decade without significant settling time degradation. Experimental results for a prototype fabricated in an AMI 0.5-/spl mu/m CMOS process show DC gain of around 90 dB and a 1% settling time of 15 ns for a load capacitor of 12 pF. The power supply used is /spl plusmn/1.25 V.

A robust feedforward compensation scheme for multistage operational transconductance amplifiers with no Miller capacitors

A novel damping-factor-control frequency compensation (DFCFC) technique is presented in this paper with detailed theoretical analysis, This compensation technique improves frequency response, transient response, and power supply rejection for amplifiers, especially when driving large capacitive loads, Moreover, the required compensation capacitors are small and can be easily integrated in commercial CMOS process. Amplifiers using DFCPC and nested Miller compensation (NMC) driving two capacitive loads, 100 and 1000 pF, were fabricated using a 0.8-/spl mu/m CMOS process with V/sub tn/=0.72 V and V/sub tp/=-0.75 V. For the DFCFC amplifier driving a 1000-pF load, a 1-MHz gain-bandwidth product, 51/spl deg/ phase margin, 0.33-V//spl mu/s slew rate, 3.54-/spl mu/s settling time, and 426-/spl mu/W power consumption are obtained with integrated compensation capacitors. Compared to the NMC amplifier, the frequency and transient responses of the DFCFC amplifier are improved by one order of magnitude with insignificant increase of the power consumption.

Three-stage large capacitive load amplifier with damping-factor-control frequency compensation

An active-feedback frequency-compensation (AFFC) technique for low-power operational amplifiers is presented in this paper. With an active-feedback mechanism, a high-speed block separates the low-frequency high-gain path and high-frequency signal path such that high gain and wide bandwidth can be achieved simultaneously in the AFFC amplifier. The gain stage in the active-feedback network also reduces the size of the compensation capacitors such that the overall chip area of the amplifier becomes smaller and the slew rate is improved. Furthermore, the presence of a left-half-plane zero in the proposed AFFC topology improves the stability and settling behavior of the amplifier. Three-stage amplifiers based on AFFC and nested-Miller compensation (NMC) techniques have been implemented by a commercial 0.8-/spl mu/m CMOS process. When driving a 120-pF capacitive load, the AFFC amplifier achieves over 100-dB dc gain, 4.5-MHz gain-bandwidth product (GBW) , 65/spl deg/ phase margin, and 1.5-V//spl mu/s average slew rate, while only dissipating 400-/spl mu/W power at a 2-V supply. Compared to a three-stage NMC amplifier, the proposed AFFC amplifier provides improvement in both the GBW and slew rate by 11 times and reduces the chip area by 2.3 times without significant increase in the power consumption.

Active-feedback frequency-compensation technique for low-power multistage amplifiers

The use of two frequency compensation schemes for three-stage operational transconductance amplifiers, namely the reversed nested Miller compensation with nulling resistor (RN-MCNR) and reversed active feedback frequency compensation (RAFFC), is presented in this paper. The techniques are based on the basic RNMC and show an inherent advantage over traditional compensation strategies, especially for heavy capacitive loads. Moreover, they are implemented without entailing extra transistors, thus saving circuit complexity and power consumption. A well-defined design procedure, introducing phase margin as main design parameter, is also developed for each solution. To verify the effectiveness of the techniques, two amplifiers have been fabricated in a standard 0.5-mum CMOS process. Experimental measurements are found in good agreement with theoretical analysis and show an improvement in small-signal and large-signal amplifier performances. Finally, an analytical comparison with the nonreversed counterparts topologies, which shows the superiority of the proposed solutions, is also included.

Advances in Reversed Nested Miller Compensation

The design considerations for fast-settling operational amplifiers (op amps) are significantly different between sampled-data switched-capacitor (SC) and conventional continuous-time applications. In SC circuits, the shape of the output voltage waveform of an op amp is of no consequence provided that the output settles to within a specified tolerance of its steady-state value prior to the next sampling instant. This feature allows for an optimum op amp frequency shaping to obtain a minimum small-signal settling time. The theory applies to any op amp that is well approximated by a two-pole model, including the conventional two-stage and single-stage folded-cascode topologies. As the commonly used equivalent-circuit Miller-effect model for frequency compensation has generally been improperly applied to two-stage transconductance amplifiers, it does not provide sufficient accuracy to achieve the optimum phase margin condition. Therefore, the use of equivalent-circuit models has been refined to provide greater accuracy and to eliminate some previous misconceptions. >

Considerations for fast settling operational amplifiers

An MOS cascode current source that employs both active and passive series feedback is reported. Small-signal analysis and SPICE simulation results show that a CMOS implementation of the active-feedback cascode current source provides an output open-circuit Thevinin voltage greater than 10/sup 6/ V. This represents an increase of about two orders of magnitude as compared with the conventional cascode current source. The active-feedback cascode current source maintains the same output voltage swing range as the conventional double cascode. >

H.C. Yang

Papers

Considerations for fast settling operational amplifiers

An active-feedback cascode current source