Publisher Summary This chapter presents and compares two statistical approaches to computer experiments. The second approach does so by taking random input points. Randomness is required to generate probability or confidence intervals. The first approach introduces randomness by modeling the function, f, as a realization of a Gaussian process. Deterministic computer simulations of physical phenomena are becoming widely used in science and engineering. Some of the most widely used computer models arise in the design of the semiconductors used in the computers themselves. There are two main statistical approaches to computer experiments, one based on Bayesian statistics and a frequentist one based on sampling techniques. A Bayesian approach to modeling simulator output can be based on a spatial model adapted from the geo-statistical Kriging model. This approach treats the bias or systematic departure of the response surface from a linear model as the realization of a stationary random function. This model has exact predictions at the observed responses and predicts with increasing error variance as the prediction point moves away from all the design points.

9 Computer experiments

First introduced in 1965, the concept of a "desirability function" has gained wide acceptance as a method of determining parameter settings to optimize a process with multiple output measurements. Unfortunately, little attention has been paid to the underlying assumptions of decision theory on which the procedure is based. This paper demonstrates critical issues that can arise from blind adherence to this procedure.

"The desirability function: underlying assumptions and application implications"

This paper presents an overview of methods to automatically generate posynomial response surface models for the performance characteristics of analog integrated circuits based on numerical simulation data. The methods are capable of generating posynomial performance expressions for both linear and nonlinear circuits and circuit characteristics, at SPICE-level accuracy. This approach allows for automatic generation of an accurate sizing model for a circuit that composes a geometric program that fully describes the analog circuit sizing problem. The automatic generation avoids the time-consuming and approximate nature of handcrafted analytic model generation. The methods are based on techniques from design of experiments and response surface modeling. Attention is paid to estimating the relative "goodness-of-fit" of the generated models. Experimental results illustrate the capabilities and effectiveness of the presented methods.

Simulation-based generation of posynomial performance models for the sizing of analog integrated circuits

Spin-torque transfer magnetic RAM (STT MRAM) is a promising candidate for future embedded applications. It combines the desirable attributes of current memory technologies such as SRAM, DRAM, and flash memories (fast access time, low cost, high density, and non-volatility). It also solves the critical drawbacks of conventional MRAM technology: poor scalability and high write current. However, variations in process parameters can lead to a large number of cells to fail, severely affecting the yield of the memory array. In this paper, we analyzed and modeled the failure probabilities of STT MRAM cells due to parameter variations. Based on the model, we performed a thorough analysis of the impact of design parameters on parametric failures due to process variations. To achieve high memory yield without incurring expensive technology modification, we developed an efficient design paradigm from circuit and/or architecture perspective-to improve the robustness and integration density. The proposed technique effectively relaxes or completely decouples the conflicting design requirements for read stability, writability and cell area. It can be used at an early stage of the design cycle for yield enhancement.

Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective

The introduction of simulation-based analog synthesis tools creates a new challenge for analog modeling. These tools routinely visit 10/sup 3/ to 10/sup 5/ fully simulated circuit solution candidates. What might we do with all this circuit data? We show how to adapt recent ideas from large-scale data mining to build models that capture significant regions of this visited performance space, parameterized by variables manipulated by synthesis, trained by the data points visited during synthesis. Experimental results show that we can automatically build useful nonlinear regression models for large analog design spaces.

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Remembrance of circuits past: macromodeling by data mining in large analog design spaces

A statistically oriented methodology for optimization and sensitivity analysis of VLSI process, device, and circuit design through computer simulation has been developed. Emphasis has been placed on maintaining a clear distinction between design synthesis and design analysis. Design analysis is viewed as a multiple input-output system resulting in a multiple-constraints-optimization problem. It is shown how simple graphic techniques or rigorous mathematical optimization can be performed within a constrained desirability space to determine optimal operating conditions. This leads directly to the concept of global input factors. Which affect a large number of the response variables, and specific input factors, which can be used to adjust the operating level of a small number of response variables. By using the derived empirical equations to desensitize the responses to variations in input factors, the proposed methodology can play a key role in designing for manufacturability. As proof of concept, the methodology has been applied to the optimization of a VLSI BIMOS technology, with satisfactory results. >

Application of statistical design and response surface methods to computer-aided VLSI device design

Methodology which incorporates the philosophy and methods of Taguchi is developed to address the issues of designing for manufacturability and sensitivity analysis. Specifically, the goal is to obtain responses (outputs) at or near required targets and to minimize output variability when the inputs are subject to manufacturing tolerances. The desirability functions, which generalize the notion of yield, are used to assess how close responses are to their targets. Manufacturing tolerances in the inputs are incorporated in the analysis by means of the expected loss of the desirability function which is estimated by a Taguchi outer array approach. The desirability expected loss is used to determine an optimum nominal input point to give responses close to target with small variability. The sensitivity of the various responses to the inputs is determined by an analytical method and an analysis of variance approach using a Taguchi outer array. The methods are applied to the optimization of a BIMOS NPN transistor. >

H.D. Weed

Papers

Application of statistical design and response surface methods to computer-aided VLSI device design

Application of statistical design and response surface methods to computer-aided VLSI device design II. Desirability functions and Taguchi methods