VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.

· Most up-to-date coverage of design for testability. 
· Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. 
· Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
· Lecture slides and exercise solutions for all chapters are now available.
· Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.

Table of Contents

Chapter 1 - Introduction
Chapter 2 - Design for Testability
Chapter 3 - Logic and Fault Simulation 
Chapter 4 - Test Generation 
Chapter 5 - Logic Built-In Self-Test
Chapter 6 - Test Compression
Chapter 7 - Logic Diagnosis
Chapter 8 - Memory Testing and Built-In Self-Test
Chapter 9 - Memory Diagnosis and Built-In Self-Repair
Chapter 10 - Boundary Scan and Core-Based Testing
Chapter 11 - Analog and Mixed-Signal Testing
Chapter 12 - Test Technology Trends in the Nanometer Age

VLSI Test Principles and Architectures: Design for Testability

An overview of built-in self-test (BIST) principles and practices is presented. The issues and economics underlying BIST are discussed, and the related hierarchical test structures are introduced. The fundamental BIST concepts of pattern generation and response analysis are explained. Linear feedback shift register theory is reviewed. >

A tutorial on built-in self-test. I. Principles

For pt.1 see ibid., vol.10, no.1, p.73-82 (1993). The hardware structures and tools used to implement built-in self-test (BIST) pattern generation and response analysis concepts are reviewed. The authors describe testing approaches for general and structured logic, including ROMs, RAMs, and PLAs. They illustrate BIST techniques with real-world examples. >

A tutorial on built-in self-test. 2. Applications

This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI practitioners and researchers in need of fluency in an "adjacent" field will find this an invaluable reference to the basic EDA concepts, principles, data structures, algorithms, and architectures for the design, verification, and test of VLSI circuits. Anyone who needs to learn the concepts, principles, data structures, algorithms, and architectures of the EDA flow will benefit from this book.


Covers complete spectrum of the EDA flow, from ESL design modeling to logic/test synthesis, verification, physical design, and test - helps EDA newcomers to get "up-and-running" quickly 
Includes comprehensive coverage of EDA concepts, principles, data structures, algorithms, and architectures - helps all readers improve their VLSI design competence 
Contains latest advancements not yet available in other books, including Test compression, ESL design modeling, large-scale floorplanning, placement, routing, synthesis of clock and power/ground networks - helps readers to design/develop testable chips or products 
Includes industry best-practices wherever appropriate in most chapters - helps readers avoid costly mistakes



Table of Contents


Chapter 1: Introduction Chapter 2: Fundamentals of CMOS Design Chapter 3: Design for Testability Chapter 4: Fundamentals of Algorithms Chapter 5: Electronic System-Level Design and High-Level Synthesis Chapter 6: Logic Synthesis in a Nutshell Chapter 7: Test Synthesis Chapter 8: Logic and Circuit Simulation Chapter 9:?Functional Verification Chapter 10: Floorplanning Chapter 11: Placement Chapter 12: Global and Detailed Routing Chapter 13: Synthesis of Clock and Power/Ground Networks Chapter 14: Fault Simulation and Test Generation.

Electronic Design Automation: Synthesis, Verification, and Test

In this paper, novel and optimized test strategies are presented for the generation of a set of predetermined test vectors on chip to be used as part of a BIST strategy for complex programmable data paths. Starting from a set of faults and a corresponding set of test vectors that cover these faults, the corresponding self-test hardware is determined automatically. For this purpose, a cellular automaton has been made. The CAD tool CAST accomplishes the synthesis of the cellular automaton and the self-test control logic, and evaluates the solution obtained. Dedicated test strategies for 1-pattern tests on the one hand and 1- and 2-pattern tests on the other hand have been developed. These new optimized strategies guarantee a BIST implementation with 100% stuck-at and stuck-open/close fault coverage for all detectable faults. They have been applied to data paths as used in an industrial-size speech processing vocoder design, developed with the silicon compiler CATHEDRAL-II. >

Cellular automata based deterministic self-test strategies for programmable data paths

The authors present a method for fully testing chips designed using synthesis and silicon compilation. The method is targeted for a multiprocessor architecture that implements low-speed to medium-speed signal-processing algorithms. By taking advantage of the specific properties of the architecture, the method allows a chip to be partitioned into several functional units. The authors use the C-test concept instead of the traditional automatic test-pattern generation to derive a compact set of test vectors. The fault model covers both the stuck-at class and part of the transistor stuck-open and stuck-closed cases. For large units with embedded memory, the authors adopt a self-test approach. >

A testability strategy for microprocessor architecture

A novel method for the generation of a set of predetermined test vectors on chip to be used as part of a BIST (built-in self-test) strategy for a class of data paths is presented. Given a set of faults and a corresponding set of test vectors which cover these faults, the corresponding self-test hardware will be generated automatically. For this purpose, use has been made of a cellular automaton which can be toggled between two rules. The CAD (computer-aided-design) program CAST accomplishes the synthesis of the cellular automaton, and the method has been applied to a data path used in the Cathedral-II/second silicon compilation environment. This technique makes it possible to obtain a BIST implementation with 100% stuck-at and stuck-open/close fault coverage for all detectable faults at the cost of an area overhead which is larger than that of conventional LFSR-(linear-feedback-shift-register) based methods but which is still acceptable. >

Cellular automata based self-test for programmable data paths

A testability strategy is presented for registers and memories embedded in multiprocessor chips designed with the Cathedral-II silicon compilation environment. The implementation requires the design of a scan register that is able to maintain a value at its output while scanning a vector into the scan chain. A test algorithm for the register file, based on the concept of C-testability, is derived. The fault model covers both stuck-at and most of the transistor stuck-open and stuck-close cases. In addition, large embedded memories are important in processor systems. A test strategy with very high fault coverage is implemented with a self-test approach. >

H. De Man

Papers

Cellular automata based deterministic self-test strategies for programmable data paths

A testability strategy for microprocessor architecture

Cellular automata based self-test for programmable data paths

Testability strategy for registers and memories in a multi-processor architecture