Some adaptive signal processing applications, such as wideband active noise control and acoustic echo cancellation, involve adaptive filters with hundreds of taps. The computational burden associated with these long adaptive filters precludes their use for many low-cost applications. In addition, adaptive filters with many taps may also suffer from slow convergence, especially if the reference signal spectrum has a large dynamic range. Subband techniques have been previously developed for adaptive filters to solve these problems. However, the conventional approach is ruled out for many applications because delay is introduced into the signal path. The paper presents a new type of subband adaptive filter architecture in which the adaptive weights are computed in subbands, but collectively transformed into an equivalent set of wideband filter coefficients. In this manner, signal path delay is avoided while retaining the computational and convergence speed advantages of subband processing. An additional benefit accrues through a significant reduction of aliasing effects. An example of the general technique is presented for a 32-subband design using a polyphase FFT implementation. For this example, the number of multiplies required are only about one-third that of a conventional full band design with zero delay, and only slightly greater than that of a conventional subband design with 16 ms delay. >

A delayless subband adaptive filter architecture

In this paper, we present an efficient distributed-arithmetic (DA) formulation for the implementation of block least mean square (BLMS) algorithm. The proposed DA-based design uses a novel look-up table (LUT)-sharing technique for the computation of filter outputs and weight-increment terms of BLMS algorithm. Besides, it offers significant saving of adders which constitute a major component of DA-based structures. Also, we have suggested a novel LUT-based weight updating scheme for BLMS algorithm, where only one set of LUTs out of M sets need to be modified in every iteration, where N=ML, N, and L are, respectively, the filter length and input block-size. Based on the proposed DA formulation, we have derived a parallel architecture for the implementation of BLMS adaptive digital filter (ADF). Compared with the best of the existing DA-based LMS structures, proposed one involves nearly L/6 times adders and L times LUT words, and offers nearly L times throughput of the other. It requires nearly 25% more flip-flops and does not involve variable shifters like those of existing structures. It involves less LUT access per output (LAPO) than the existing structure for block-size higher than 4. For block-size 8 and filter length 64, the proposed structure involves 2.47 times more adders, 15% more flip-flops, 43% less LAPO than the best of existing structures, and offers 5.22 times higher throughput. The number of adders of the proposed structure does not increase proportionately with block size; and the number of flip-flops is independent of block-size. This is a major advantage of the proposed structure for reducing its area delay product (ADP); particularly, when a large order ADF is implemented for higher block-sizes. ASIC synthesis result shows that, the proposed structure for filter length 64, has almost 14% and 30% less ADP and 25% and 37% less EPO than the best of the existing structures for block size 4 and 8, respectively.

A High-Performance Energy-Efficient Architecture for FIR Adaptive Filter Based on New Distributed Arithmetic Formulation of Block LMS Algorithm

This brief presents a novel pipelined architecture for low-power, high-throughput, and low-area implementation of adaptive filter based on distributed arithmetic (DA). The throughput rate of the proposed design is significantly increased by parallel lookup table (LUT) update and concurrent implementation of filtering and weight-update operations. The conventional adder-based shift accumulation for DA-based inner-product computation is replaced by conditional signed carry-save accumulation in order to reduce the sampling period and area complexity. Reduction of power consumption is achieved in the proposed design by using a fast bit clock for carry-save accumulation but a much slower clock for all other operations. It involves the same number of multiplexors, smaller LUT, and nearly half the number of adders compared to the existing DA-based design. From synthesis results, it is found that the proposed design consumes 13% less power and 29% less area-delay product (ADP) over our previous DA-based adaptive filter in average for filter lengths N = 16 and 32. Compared to the best of other existing designs, our proposed architecture provides 9.5 times less power and 4.6 times less ADP.

Low-Power, High-Throughput, and Low-Area Adaptive FIR Filter Based on Distributed Arithmetic

In this paper, we propose an efficient systolic architecture for the delay least-mean-square (DLMS) adaptive finite impulse response (FIR) digital filter based on a new tree-systolic processing element (PE) and an optimized tree-level rule. Applying our tree-systolic PE, a higher convergence rate than that of the conventional DLMS structures can be obtained without sacrificing the properties of the systolic-array architecture. The efficient systolic adaptive FIR digital filter not only operates at the highest throughput in the word-level but also considers finite driving/update of the feedback error signal. Furthermore, based on our proposed optimized tree-level rule that takes account of minimum delay and high regularity, an efficient N-tap systolic adaptive FIR digital filter can be easily determined under the constraint of maximum driving of the feedback error signal.

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An efficient systolic architecture for the DLMS adaptive filter and its applications

A method is presented for analyzing the stability and transient response of the filtered-x LMS adaptive notch filter by formulating the problem in the complex weight domain and applying standard control theory. Examples are given for pure delay and second-order low-pass cancellation path transfer functions. The method is also extended to the multichannel case, where the eigenvalues of the equivalent open-loop transfer function matrix characterize the behavior. >

A control theory approach to the stability and transient analysis of the filtered-x LMS adaptive notch filter

A systolic array design for an adaptive filter is presented. The filter is based on the least-mean-square algorithm, but due to the problems in implementation of the systolic array, a modified algorithm, a special case of the delayed LMS (DLMS), is used. The DLMS algorithm introduces a delay in the updating of the filter coefficients. The convergence and steady-state behavior of the systolic array are analyzed. It is shown that the performance of the systolic array is similar to that of a conventional LMS implementation for a wide range of practical conditions. >

A systolic array realization of an LMS adaptive filter and the effects of delayed adaptation

The main results are presented of an analysis of the convergence and the steady-state behavior of the DLMS (delayed least mean square) algorithm, with the aim of providing useful insight which may be helpful in the design of such filters. The problem is defined, and some basic definitions are presented. Conditions for convergence, convergence rate, and limits are discussed. Remarks are presented. The implications of the results for the design of DLMS adaptive filters are addressed. >

H. Herzberg

Papers

A systolic array realization of an LMS adaptive filter and the effects of delayed adaptation

Delayed adaptive LMS filtering: current results