The phase-shifting mask consists of a normal transmission mask that has been coated with a transparent layer patterned to ensure that the optical phases of nearest apertures are opposite. Destructive interference between waves from adjacent apertures cancels some diffraction effects and increases the spatial resolution with which such patterns can be projected. A simple theory predicts a near doubling of resolution for illumination with partial incoherence σ < 0.3, and substantial improvements in resolution for σ < 0.7. Initial results obtained with a phase-shifting mask patterned with typical device structures by electron-beam lithography and exposed using a Mann 4800 10× tool reveals a 40-percent increase in usuable resolution with some structures printed at a resolution of 1000 lines/mm. Phase-shifting mask structures can be used to facilitate proximity printing with larger gaps between mask and wafer. Theory indicates that the increase in resolution is accompanied by a minimal decrease in depth of focus. Thus the phase-shifting mask may be the most desirable device for enhancing optical lithography resolution in the VLSI/VHSIC era.

Improving resolution in photolithography with a phase-shifting mask

A method and apparatus for creating a phase shifting mask and a structure mask for shrinking integrated circuit designs. One embodiment of the invention includes using a two mask process. The first mask is a phase shift mask and the second mask is a single phase structure mask. The phase shift mask primarily defines regions requiring phase shifting. The single phase structure mask primarily defines regions not requiring phase shifting. The single phase structure mask also prevents the erasure of the phase shifting regions and prevents the creation of undesirable artifact regions that would otherwise be created by the phase shift mask. Both masks are derived from a set of masks used in a larger minimum dimension process technology.

Phase shifting circuit manufacture method and apparatus

A method for performing design rule checking on OPC corrected or otherwise corrected designs is described. This method comprises accessing a corrected design and generating a simulated image. The simulated image corresponds to a simulation of an image which would be printed on a wafer if the wafer were exposed to an illumination source directed through the corrected design. The characteristics of the illumination source are determined by a set of lithography parameters. In creating the image, additional characteristics can be used to simulate portions of the fabrication process. However, what is important is that a resulting simulated image is created. The simulated image can then be used by the design rule checker. Importantly, the simulated image can be processed to reduce the number of vertices in the simulated image, relative to the number of vertices in the OPC corrected design layout. Also, the simulated image can be compared with an idea layout image, the results of which can then be used to reduce the amount of information that is needed to perform the design rule checking.

Design rule checking system and method

A method and apparatus for the correction of integrated circuit layouts for optical proximity effects which maintains the original true hierarchy of the original layout is provided. Also provided is a method and apparatus for the design rule checking of layouts which have been corrected for optical proximity effects. The OPC correction method comprises providing a hierarchically described integrated circuit layout as a first input (205), and a particular set of OPC correction criteria as a second input (260). The integrated circuit layout is then analyzed to identify features of the layout which meet the provided OPC correction criteria (210, 240). After the areas on the mask which need correction have been identified (310), optical proximity correction data (320) is generated in response to the particular set of correction criteria. Finally, a first program data is generated which stores the generated optical proximity correction data in a hierarchical structure (320) that corresponds to the hierarchical structure of the integrated circuit layout (310). As the output correction data is maintained in true hierarchical format, layouts which are OPC corrected according to this method are able to be processed through conventional design rule checkers with no altering of the data.

Data hierarchy layout correction and verification method and apparatus

Techniques are provided for extending the use of phase shift techniques to implementation of masks used for complex layouts in the layers of integrated circuits, beyond selected critical dimension features. The method includes identifying features for which phase shifting can be applied, automatically mapping the phase shifting regions for implementation of such features, resolving phase conflicts which might occur according to a given design rule, and application of assist features and proximity correction features. The method includes applying an adjustment to a phase shift mask pattern including a first and a second phase shift window, and a control chrome with a control width, and/or to a trim mask pattern having a trim shape with a trim width based upon one or both of a rule based correction and a model based correction to improve a match between a resulting exposure pattern and a target feature.

Phase shift masking for complex patterns with proximity adjustments

A blind mask and a simplified-blind (S-blind) mask proposed for phase shifting lithography are discussed. They both have very simple structures. Both the blind and S-blind methods are very effective in solving the bridging problem in single-layer-shifter phase-shifting lithography. These phase-shifting methods are suitable for 0.3- mu m lithography for the manufacture of 64-Mb DRAMs. >

Application of blind method to phase-shifting lithography

Copper is the major candidate material of post-Al alloys in deep sub-micron region, because of low resistivity and long electromigration lifetime. Recently, ion milling and chemical mechanical polishing (CMP) have been applied to fine Cu interconnects, and these techniques can avoid the difficulty of etching Cu caused by hardly subliming etching-products. However, these are not necessarily the well-established technique for ULSI process. Our approach is modification of the high temperature dry etching, which includes the self-aligned passivation technique. In this work, we have formed TiN/Cu/TiN multilayered interconnects of sub-quarter micron width using the modified dry etching technique, and evaluated the resistance to electromigration damage (EMD). >

H. Jinbo

Papers

Application of blind method to phase-shifting lithography

Sub-quarter micron copper interconnects through dry etching process and its reliability