THE theory of Fourier integrals arises out of the elegant pair of reciprocal formulae The Laplace Transform By David Vernon Widder. (Princeton Mathematical Series.) Pp. x + 406. (Princeton: Princeton University Press; London: Oxford University Press, 1941.) 36s. net.

The Laplace Transform

Contents: Transition Functions and Resolvents.- Existence and Uniqueness of Q-Functions.- Examples of Continuous Time Markov Chains.- More on the Uniqueness Problem.- Classification of States and Invariant Measures.- Strong and Exponential Ergodicity.- Reversibility, Monotonictity, and Other Properties.- Birth and Death Processes.- Population Processes.- Bibliography.- Symbol Index.- Author Index.- Subject Index.

Book Reviews - Continuous Time Markov Chains: An Applications-Oriented Approach

The central theme of our work is the probabilistic and approximate design of embedded computing systems. This novel approach consists of two distinguishing aspects: (i) the design and implementation of embedded systems, using components which are susceptible to perturbations from various sources and (ii) a design methodology which consists of an exploration of a design space which characterizes the trade-off between quality of output and cost, to implement high performance and low energy embedded systems. In contrast with other work, our design methodology does not attempt to correct the errors introduced by components which are susceptible to perturbations, instead we design "good enough" systems. Our work has the potential to address challenges and impediments to Moore's law arising from material properties and manufacturing difficulties, which dictate that we shift from the current-day deterministic design paradigm to statistical and probabilistic designs of the future. In this paper, we provide a broad overview of our work on probabilistic and approximate design, present novel results in approximate arithmetic and its impact on digital signal processing algorithms, and sketch future directions for research.

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Sustaining moore's law in embedded computing through probabilistic and approximate design: retrospects and prospects

As the size of CMOS devices is scaled down to nanometers, noise can significantly affect circuit performance. Because noise is random and dynamic in nature, a probabilistic-based approach is better suited to handle these types of errors compared with conventional CMOS designs. In this paper, we propose a cost-effective probabilistic-based noise-tolerant circuit-design methodology. Our cost-effective method is based on master-and-slave Markov random field (MRF) mapping and master-and-slave MRF logic-gate construction. The resulting probabilistic-based MRF circuit trades hardware cost for circuit reliability. To demonstrate a noise-tolerant performance, an 8-bit MRF carry-lookahead adder (MRF_CLA) was implemented using the 0.13-mum CMOS process technology. The chip measurement results show that the proposed master-and-slave MRF_CLA can provide a 7.00 times 10-5 bit-error rate (BER) under 10.6-dB signal-to-noise ratio, while the conventional CMOS_CLA can only provide 8.84 times 10-3 BER. Because of high noise immunity, the master-and-slave MRF_CLA can operate under 0.25 V to tolerate noise interference with only 1.9 muW/MHz of energy consumption. Moreover, the transistor count can be reduced by 42% as compared with the direct-mapping MRF_CLA design .

Design and Implementation of Cost-Effective Probabilistic-Based Noise-Tolerant VLSI Circuits

Ultra-low-power systems with substantial computing capacity require latches and SRAMs to operate at extremely low supply voltages. However, with aggressive technology scaling, reliability becomes a major challenge due to unavoidable process variations and the presence of multiple noise sources, including intrinsic thermal noise. This paper provides a quantitative measure of reliability by calculating the probability distribution function (PDF) of errors induced by thermal noise in latches and SRAMs operating in subthreshold conditions. Implemented in a novel simulation tool for thermal-noise analysis of CMOS circuits (STTACC), our algorithm uses a stochastic differential equation circuit model that preserves the proper Poissonian statistics for thermal-noise-driven current fluctuations in MOSFETs. Our probabilistic error model can handle error rate analysis for arrays of latches or full SRAMs on time scales from seconds to years without excessive computational overhead. We demonstrate that the time-to-error (TTE) statistics of subthreshold SRAMs obey log-normal distributions that depend on parameters such as node and device capacitance, device threshold variations and operating conditions of supply voltage and temperature. This makes it possible to quantitatively evaluate the asymptotic behavior of extremely rare error events that are inaccessible to standard SPICE-based simulations.

Fundamental Thermal Limits on Data Retention in Low-Voltage CMOS Latches and SRAM

Electrical noise will play an increasingly critical role in future nanoscale CMOS circuit operation character ized by lower supply voltages VDD and smaller device sizes. Both of these downscaling approaches reduce the margin of immunity to thermal noise, alpha particle strikes, and threshold voltage variations. This paper investigates the noise probability distributions for both equilibrium and non-equilibrium logic states of advanced CMOS flip-flops operated at ultra-low VDD. The theoretical distribution of transition times from one stable operation point to the other stable operation point is also der ived, which is a useful representation of the soft error rate. It is shown that such nanoscale flip-flop designs are extremely sensitive to threshold variations, reducing average failure time to a few days. Monte Carlo simulations are provided to validate the theoretical model and its predictions.

H. Li

Papers

Thermally-induced soft errors in nanoscale CMOS circuits