Structures and methods for CMOS gate arrays with vertical transistors are provided. The CMOS gate arrays with vertical transistors comprise a logic circuit. The logic circuit includes a dynamic pull-down circuit having a number of logic inputs, a clock input, and an output. The number of logic inputs are coupled to a number of gates of free standing vertical n-channel transistors. The clock input is coupled to a gate of a free standing vertical p-channel transistor for precharging the output. The logic circuit further includes a static pull-up circuit having a number of logic inputs, a clock bar input, and an output. The number of logic inputs are coupled to a number of gates of free standing vertical n-channel transistors. The clock bar input is coupled to a gate of a free standing vertical n-channel transistor for precharging the output. And, the dynamic pull down circuit is cascaded with the static pull up circuit such that one of the number of inputs for the pull up circuit is coupled to the output of the pull down circuit.

CMOS gate array with vertical transistors

Structures and methods for pseudo-CMOS dynamic logic with delayed clocks are provided. A pseudo-CMOS dynamic logic circuit with delayed clocks includes a dynamic pseudo-nMOS logic gate and a dynamic pseudo-pMOS logic gate coupled thereto. The dynamic pseudo-nMOS logic gate includes a delayed enable clock transistor coupled to a source region of at least two input transistors. The dynamic pseudo-pMOS logic gate includes a delayed enable clock transistor coupled to a drain of at least two input transistors. None of the logic input devices are connected in series.

Pseudo CMOS dynamic logic with delayed clocks

A method and apparatus for evaluating logical inputs electronically using electronic logic circuits in monotonic dynamic-static pseudo-NMOS configurations. The apparatus includes alternating dynamic and static circuit portions adapted to transition monotonically in response to a common clock (or complemented clock) signal. The circuit portions include pseudo-NMOS configured switching circuits implementing logical functions.

Monotonic dynamic static pseudo-NMOS logic circuits

A new low-noise logic family is presented in which the supply current spikes due to switching are much reduced with respect to conventional CMOS circuits. A comparison with existing alternative circuits shows that, for the same supply voltage and the same power consumption, the new circuits have smaller area, higher noise margins, and lower delay.

A new low-noise logic family for mixed-signal integrated circuits

A programmable logic array (PLA) with J-K flip-flops as feedback loops and having a maximum operating speed of 12 MHz has been designed and realized in epitaxial-silicon-films-on-insulators (ESFI) silicon-on-sapphire (SOS) technology. The advantages of the ESFI SOS technology and the circuit of the PLA are described and experimental results are presented. In addition, a twin PLA using metal-nitride-oxide-semiconductor (MNOS) transistors in the AND and OR matrices and having the same number of inputs, outputs, and feedback loops as the mask-programmable PLA has been designed. This MNOS PLA has full on-chip decoding capability and can be programmed or reprogrammed individually. The circuit of the MNOS PLA is described and the speed of the device is calculated.

A high-speed ESFI SOS programmable logic array with an MNOS version

The performance of grounded load complementary MOS circuits has been evaluated. It has been found that a very significant improvement in performance and reduction in circuit-area might be achieved by employing grounded load devices in portions of a system employing large-scale integrated CMOS circuits.

H. Sakamoto

Papers

Grounded load complementary FET circuits: Sceptre analysis