In this paper, various fault location techniques in analog networks are described and compared. The emphasis is on the more recent developments in the subject. Four main approaches for fault location are addressed, examined, and illustrated using simple network examples. In particular, we consider the fault dictionary approach, the parameter identification approach, the fault verification approach, and the approximation approach. Theory and algorithms that are associated with these approaches are reviewed and problems of their practical application are identified. Associated with the fault dictionary approach we consider fault dictionary construction techniques, methods of optimum measurement selection, different fault isolation criteria, and efficient fault simulation techniques. Parameter identification techniques that either utilize linear or nonlinear systems of equations to identify all network elements are examined very thoroughly. Under fault verification techniques we discuss node-fault diagnosis, branch-fault diagnosis, subnetwork testability conditions as well as combinatorial techniques, the failure bound technique, and the network decomposition technique. For the approximation approach we consider probabilistic methods and optimization-based methods. The artificial intelligence technique and the different measures of testability are also considered. The main features of the techniques considered are summarized in a comparative table. An extensive, but not exhaustive, bibliography is provided.

Fault diagnosis of analog circuits

Traditionally, work on analog testing has focused on diagnosing faults in board designs. Recently, with increasing levels of integration, not just diagnosing faults, but distinguishing between faulty and good circuits has become a problem. Analog blocks embedded in digital systems may not easily be separately testable. Consequently, many papers have been recently written proposing techniques to reduce the burden of testing analog and mined-signal circuits. This survey attempts to outline some of this recent work, ranging from tools for simulation-based test set development and optimization to built-in self-test (BIST) circuitry.

A tutorial introduction to research on analog and mixed-signal circuit testing

A simulation-after-test algorithm for the analog fault diagnosis problem is proposed in which a bound on the maximum number of simultaneous failures is used to minimize the number of test points required. The resultant algorithm is applicable to both linear and nonlinear systems with multiple hard or soft faults and can be used to isolate failures up to an arbitrarily specified "replaceable chip or subsystem."

Analog Fault Diagnosis with Failure Bounds

This paper proposes and proves an important theorem and its corollary for linear analog circuits, i.e., the invariance of the node-voltage sensitivity sequence and the invariance of the node-voltage change sequence. Based on them, a unified fault detection dictionary method for both hard and soft faults in analog circuits is proposed. This method uses only one fault characteristic code to detect any hard or soft fault of any component. In addition, the size of the dictionary is only one half of that of the original hard fault dictionary.

The invariance of node-voltage sensitivity sequence and its application in a unified fault detection dictionary method

A fault detection method, i.e. the short-circuit admittance parameters method, for linear analog ICs is proposed in this paper. Only two voltage measurements at the ports of the circuit are suggested to decide whether the circuit is working normally. This method can be used to design automatic circuit fault detection equipment for technicians to decide whether there are any faults in linear analog circuits. The attractive merits of this method are component parameter tolerance and error reduction in measurement and calculation.

Fault detection for linear analog IC-the method of short-circuit admittance parameters

A method of fault signature generation is presented that is based upon state space analysis of linear circults. An input control sequence is designed to reduce a nontrivial initial state of the circuit under test to the zero state in finite time. The realization of this stimulus as a piecewise constant waveform has step amplitudes that are exponential functions of the poles of the circuit under test. Perturbations of these amplitudes, engendered by element drift failure, constitute a fault signature. Single element value perturbations engender fault signature trajectories in signal space, and the fault dictionary is constructed by defining disjoint decision regions (hypervolumes) around each fault signature trajectory in the signal space. Circuit zeros of transmission allow the dimension of the signal space to be augmented with perturbation of such response waveform parameters as zero crossings. The theory of stimulus design for fault isolation in linear networks and a generalized matrix inverse method for computing the stimulus amplitudes from the pulse response of strictly proper circuits are presented. Examples of response waveforms and fault signature trajectories are given for several circuits.

H. Schreiber

Papers

Fault dictionary based upon stimulus design