A switch, switched architecture and process for transferring data through an FCAL switch is disclosed. The switch uses multiple switch control circuits each coupled to one FCAL network and all connected to a crossbar switch. The switch control circuits are coupled together by a protocol bus for coordination purposes. Local conversations can occur on each FCAL loop and crossing conversations through the switch can occur concurrently. The OPN primitive is used to establish the connection before any data is transferred thereby eliminating the need for buffer memory in the switch control circuits. The destination address of each OPN is used to address a lookup table in each switch control circuit to determine if the destination node is local. If not, the destination is looked up and a connection request made on the protocol bus. If the remote port is not busy, it sends a reply which causes both ports to establish a data path through the backplane crossbar switch.

Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost

Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.

Multi-pair gigabit ethernet transceiver

A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase

Phase interpolator device and method

Aspects of the invention may comprise receiving an incoming TCP packet at a TEEC (270) and processing at least a portion of the incoming packet once by the TEEC (270) without having to do any reassembly and/or retransmission by the TEEC (270). At least a portion of the incoming TCP packet may be buffered in at least one internal elastic buffer (280,290) of the TEEC (270). The internal elastic buffer (280,290) may comprise a receive internal elastic buffer (290) and/or a transmit internal elastic buffer (280). Accordingly, at least a portion of the incoming TCP packet may be buffered in the receive internal elastic buffer (290). At least a portion of the processed incoming packet may be placed in a portion of a host memory (230) for processing by a host processor or CPU (210). Furthermore, at least a portion of the processed incoming TCP packet may be DMA transferred to a portion of the host memory (230).

System and method for TCP offload

Systems and methods for network interfacing may include a communication data center with a first tier, a second tier and a third tier. The first tier may include a first server with a first single integrated convergent network controller chip. The second server may include a second server with a second single integrated convergent network controller chip. The third tier may include a third server with a third single integrated convergent network controller chip. The second server may be coupled to the first server via a single fabric with a single connector. The third server may be coupled to the second server via the single fabric with the single connector. The respective first, second and third server, each processes a plurality of different traffic types concurrently via the respective first, second and third single integrated convergent network chip over the single fabric that is coupled to the single connector.

System and method for network interfacing

A clock recovery circuit that can be used for recovering a clock signal from a data stream having a high data rate. The clock recovery circuit has a phase interpolator and non-linear digital to analog converters. These circuits are used to interpolate between the phases produced by a voltage controlled oscillator. A determination to advance or hinder a currently selected phase can be made using an up/down detector, a divider, and control logic. The divider can divide not only the up and down pulses produced by the up/down detector, but also the clock frequency. By dividing the clock frequency, the control logic can be designed using CMOS logic circuits.

Clock recovery circuit

This paper describes a low jitter phase-locked-loop (PLL) with a 4/sup th/ order control path, and a dual control voltage ring oscillator. Near constant voltage controlled oscillator (VCO) gain over process variations, in addition to compensation for feedback ratio variation, allows improved control of the PLL bandwidth. The PLL exhibits improved noise immunity with a wide (5:1) VCO frequency range, without the need for band switching or calibration routines. This PLL is fabricated in a 0.18 /spl mu/m CMOS logic process and exhibits <4 ps rms accumulated jitter.

An improved CMOS ring oscillator PLL with less than 4ps RMS accumulated jitter

This paper describes a 20-lane 62.5 Gb/s SerDes designed as an interface between the 40G, or quad 10G Optics, and a downstream framer device. Transmit and receive clocks are derived from an LC-based PLL with a wideband RMS jitter below 2.5 ps. Timing recovery uses a 2/sup nd/ order loop and includes over-sampled /spl Delta//spl Sigma/ techniques to achieve both narrowband filtering and excellent jitter tolerance. To support backplane applications, line driver and receiver incorporate preemphasis and equalization respectively.

A 62.5 Gb/s multi-standard SerDes IC

A system and method are provided for augmenting frequency tuning resolution in an L-C oscillatory circuit which comprises a source of electrical energy, and a tuned section energized by said source of electrical energy for oscillatory conduction of a resonant current therethrough. The tuned section includes an inductor portion extending in substantially looped manner between first and second connection points to define at least one turn. A primary capacitor portion is connected across at least a primary segment of the conductive member delineated by the first and second connection points. The tuned section further includes a secondary capacitor portion connected across a secondary segment of the conductive member intermediately tapped from the primary segment. The secondary capacitor portion defines a base tuning capacitance for the tuned section, which is down-converted to a fine tuning capacitance when reflected to a calibration capacitance of the primary capacitor portion for adjustable combination therewith.

System and method for augmenting frequency tuning resolution in L-C oscillation circuit

A 4/sup th/-order sigma-delta modulator is presented that offers significantly improved stability and SNR when the input is overloaded, compared to conventional single-bit modulators. The circuit combines the high linearity of a single-bit architecture with the increased stability of a multi-bit converter. Fabricated in a 0.13-/spl mu/m CMOS logic process, it draws 208 /spl mu/A from a 1.25 V nominal supply. Clocked at 1.5 MHz, the input bandwidth is 150 Hz-11 kHz, with an SNR of 84 dB.

H. Thompson

Papers

Clock recovery circuit

An improved CMOS ring oscillator PLL with less than 4ps RMS accumulated jitter

A 62.5 Gb/s multi-standard SerDes IC

System and method for augmenting frequency tuning resolution in L-C oscillation circuit

A low-voltage low-power sigma-delta modulator with improved performance in overload condition