Design The Division of Design educates and trains designers to create and develop concepts that optimize the function, value, and appearance of communications, products, and systems for the benefit of both industry and society. We offer a Bachelor of Design (BDes) degree in the following majors: Industrial Design, Interaction Design, and Visual Communication Design. At the graduate level, a Masters of Design (MDes) degree is available. Student Work Design Show 2016

On the Design of

This paper presents a fully implantable 100-channel neural interface IC for neural activity monitoring. It contains 100-channel analog recording front-ends, 10 multiplexing successive approximation register ADCs, digital control modules and power management circuits. A dual sample-and-hold architecture is proposed, which extends the sampling time of the ADC and reduces the average power per channel by more than 50% compared to the conventional multiplexing neural recording system. A neural amplifier (NA) with current-reuse technique and weak inversion operation is demonstrated, consuming 800 nA under 1-V supply while achieving an input-referred noise of 4.0 μVrms in a 8-kHz bandwidth and a NEF of 1.9 for the whole analog recording chain. The measured frequency response of the analog front-end has a high-pass cutoff frequency from sub-1 Hz to 248 Hz and a low-pass cutoff frequency from 432 Hz to 5.1 kHz, which can be configured to record neural spikes and local field potentials simultaneously or separately. The whole system was fabricated in a 0.18-μm standard CMOS process and operates under 1 V for analog blocks and ADC, and 1.8 V for digital modules. The number of active recording channels is programmable and the digital output data rate changes accordingly, leading to high system power efficiency. The overall 100-channel interface IC consumes 1.16-mW total power, making it the optimum solution for multi-channel neural recording systems.

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A 100-Channel 1-mW Implantable Neural Recording IC

A new high-performance CMOS current comparator is proposed. By adding two inverters in the feedback loop of Traff's comparator, the proposed comparator exhibits significant speed improvement especially for low input currents. Simulated in a 0.18 mum CMOS technology, the comparator achieves a 0.6 ns delay for a 100 nA input current at 1.8 V supply, which is about eight times faster than Traff's comparator.

High-performance CMOS current comparator

A new rail-to-rail CMOS input architecture is presented that delivers behavior nearly independent of the common-mode level in terms of both transconductance and slewing characteristics. Feedforward is used to achieve high common-mode bandwidth, and operation does not rely on analytic square law characteristics, making the technique applicable to deep submicron technologies. From the basis of a transconductor design, an asynchronous comparator and a video bandwidth op amp are also developed, providing a family of general purpose analog circuit functions which may be used in high (and low) bandwidth mixed-signal systems. Benefits for the system designer are that the need for rigorous control of common-mode levels is avoided and input signal swings right across the power supply range can be easily handled. A further benefit is that having very consistent performance, the circuits can be easily described in VHDL (or other behavioral language) to allow simulation of large mixed-signal systems. The circuits presented may be easily adapted for a range of requirements. Results are presented for representative transconductor, op amp, and comparator designs fabricated in a 0.5 /spl mu/m 3.3 V digital CMOS process.

A high bandwidth constant g/sub m/ and slew-rate rail-to-rail CMOS input circuit and its application to analog cells for low voltage VLSI systems

A new high-speed CMOS current comparator is described. By changing the buffer of an existing comparator from class B to class AB operation, voltage swings are reduced, resulting in greater speed for small input currents. Simulation results employing a 1.6 µm CMOS technology show the response time to a 0.1 µA input current to be 11 ns and the power dissipation to be 1.4 mW, resulting in a five times improvement in speed/power ratio over existing high-speed current comparators.

High performance CMOS current comparator

A novel high speed CMOS integrated current comparator structure is presented which uses a source-follower input stage and a CMOS inverter as a positive feedback. It exhibits short propagation delay and occupies a small chip area.

Novel approach to high speed CMOS current comparators

New compact switched current memory cells (CMCs) are proposed, which still maintain the properties of insensitivity to transistor mismatch, channel-length modulation and current sharing. Both class A and class AB structures are investigated, of which the former type has about the same or somewhat better performance than the ordinary memory cell, and the latter type outperforms both of them with respect to power consumption and clock feedthrough. The performance of the proposed structures when used in integrators is also shown.

Class A and AB compact switched current memory circuits

A novel pseudo-class AS low conductance fully differential switched current memory structure with high clock feedthrough (CFT) attenuation, is presented. It is designed with a 3V power supply. An integrator using the proposed structure is also presented with simulation results. >

H. Traff

Papers

Novel approach to high speed CMOS current comparators

Class A and AB compact switched current memory circuits

Novel pseudo-class AB fully differential 3V switched current system cells