For pt.I, see ibid., vol.38 no.8, pp.1852-1858, Aug. 1991. The physical effects discussed in Pt.I are classified with respect to real operation of devices in circuits from an engineer's viewpoint. Stress results from different kinds of logic stages are discussed and relations set up between static and dynamic lifetimes. It is shown that within certain limited error boundaries, the static approach is essentially valid as long as stress conditions are considered that are oriented to operation in digital logic. The transmission gate is investigated separately, because in this case specific phenomena caused by bidirectional stress must be considered. >

Dynamic degradation in MOSFET's. II. Application in the circuit environment

Hot-carrier degradation is measured and analyzed over ten orders of magnitude in time for three buried-channel p-MOSFET types with different oxide thicknesses. The effects of oxide charge and interface states are separated by using the charge-pumping technique. Two dominating effects are sufficient to account for the degradation. For worst case degradation, negative oxide charge and interface states are generated by electrons near the drain. This charge is distributed homogeneously over the oxide thickness and it attracts an inversion layer that extends the drain and reduces the effective transistor length logarithmically in time. Simultaneously, this inversion layer prevents substantial degradation related to the interface states, since it masks their effects. A simple model for the logarithmic time dependence is presented. At more negative gate voltages, holes cause interface states that reduce the transconductance with a power-law time dependence, comparable to the worst case n-MOSFET degradation. >

Time dependence of p-MOSFET hot-carrier degradation measured and interpreted consistently over ten orders of magnitude

In Chapter 1, the degradation of MOS transistors under DC stress conditions was considered. In a real circuit, however, most of the devices are operated dynamically, on account of which the degradation under AC stress conditions has gained increased attention. The most important question in these studies is whether the AC degradation can or cannot be predicted based on a set of DC degradation measurements. When the prediction based on DC measurements stands true, the AC degradation can be studied as a quasistatic process. When, however, the extrapolation turns out to be invalid, physical insight should be obtained for the deviating behavior.

Hot-Carrier Degradation During Dynamic Stress

Systematic measurements of gate current decrease and total gate current fluence performed on buried channel PMOS transistors of different technologies during aging are discussed. Correlations with usual parameter shifts are presented, allowing original investigations of saturation effects and lifetime determination. New opportunities for correlations with Q/sub BD/ measurements and injection on capacitors are opened. >

Correlation of total gate current fluence with PMOS degradation

Microelectronic device manufacture encompasses the fabrication, testing and simulation, of structures utilized in a variety of application specific integrated circuits. The fabrication of transistors, traditionally from elemental silicon wafer is conducted in a clean room environment utilizing various types of equipment. Process simulation is a critical element in facilitating the optimization of fabrication stages, confirming test results and theoretical models and providing physical insight into structural operation. TSUPREM-4 and MEDICI are two simulators that had been calibrated and used in this work. As device sizes are scaled down, novel structures are proposed such as halo (pocket), lightly doped drain (LDD) and source/drain process. In order to characterize and optimize Silterra 130 nm CMOS transistor design, TCAD simulation is done in this work and the results is compared with measured data and was verified to be in the Silterra specification range. Various doses, implant energies and tilt angle is used to upgrade the transistor performance, reduce the short channel effect and increase the transistor lifetime. Halo implant, lightly doped drain (LDD) implant and source/drain (S/D) implant is the three drain engineering structure to be characterized in this work. It is found that at certain dose, implant energy and tilt angle, the best saturation drain current, Idsat and threshold voltage, Vt that can match the specification target for NMOS and PMOS transistor can be achieved. It is also proved in this work that by using process and device simulator, the correct process can be predicted and the physical insight of the structure such as current flow lines and doping concentrations can be further analyzed. ABSTRAK Pengeluaran peranti mikroelektronik merangkumi pembuatan, menguji dan simulasi, struktur-struktur yang digunakan dalam pelbagai aplikasi khusus litar-litar bersepadu. Pembuatan transistor, terdiri daripada wafer silikon asas dikendalikan dalam satu persekitaran tempat bersih dengan menggunakan pelbagai jenis peralatan. Proses simulasi adalah satu unsur penting yang membantu dalam mengoptimumkan peringkatperingkat pembuatan, mengesahkan hasil percubaan dan model-model teori dan menyediakan fahaman secara fizikal ke atas operasi struktur. TSUPREM-4 dan MEDICI adalah dua jenis simulator yang telah ditentukurkan dan digunakan dalam tugas ini. Setelah saiz-saiz peranti telah diturunkan, struktur-struktur novel telah dicadangkan seperti proses implant halo â€˜halo (pocket)â€™, â€˜lightly doped drain (LDD)â€™ dan proses â€˜source/drainâ€™. Dalam peringkat untuk mencirikan dan mengoptimumkan rekabentuk transistor CMOS Silterra 130 nm, simulasi TCAD telah dijalankan dalam projek ini dan hasil-hasilnya telah dibandingkan dengan data yang telah diukur dan telah disahkan ia berada di dalam julat spesifikasi Silterra. Pelbagai dos, tenaga mengimplan dan sudut mengimplan digunakan untuk menaiktaraf prestasi transistor, mengurangkan kesan saluran pendek dan menambah jangka hayat transistor. Implan halo, â€˜lightly doped drain (LDD)â€™ dan proses â€˜source/drainâ€™ adalah tiga jenis struktur kejuruteraan parit yang akan dikaji dalam kerja ini. Didapati, dengan dos tertentu, tenaga implan dan sudut condong implan, arus parit tepu, Idsat dan voltan ambang, Vt yang terbaik dapat menepati sasaran spesifikasi bagi transistor NMOS dan PMOS. Dalam kerja ini ia dapat dibuktikan bahawa dengan menggunakan proses dan alat simulator, proses yang menepati spesifikasi dapat diramal dan struktur dalaman seperti aliran arus dan kepekatan pengedopan seterusnya dapat dianalisa.

Optimization and characterization of 130 nm cmos transistor design using tcad simulation

When the gate length is reduced to below 1/um, hot electron induced degradation of p-channel MOSFETs becomes a serious problem, Trapped electrons reduce the effective channel length causing reduction of absolute VT and current increase in the linear region1,2. Conventional and offset type P-MOSFETs have been analyzed under three stress conditions: (1) DC stress at maximum substrate current, (2) DC stress at high gate voltage, (3) and a novel Swap stress in which drain and source are interchanged several times during stressing. The last stress mode is relevant for P-channel pass transistors and transfer gates in P-MOS DRAMs.

H. Wendt

Papers

Sub Micron P-MOSFETs under Static and SWAP Stress