We present a realistic, yet computationally inexpensive simulation model for IEEE 802.11p radio shadowing in urban environments. Based on real world measurements using IEEE 802.11p/DSRC devices, we estimated the effect that buildings and other obstacles have on the radio communication between vehicles. Especially for evaluating safety applications in the field of Vehicular Ad Hoc Networks (VANETs), stochastic models are not sufficient for evaluating the radio communication in simulation. Motivated by similar work on WiFi measurements, we therefore created an empirical model for modeling buildings and their properties to accurately simulate the signal propagation. We validated our model using real world measurements in a city scenario for different types of obstacles. Our simulation results show a very high accuracy when compared with the measurement results, while only requiring a marginal overhead in terms of computational complexity.

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A computationally inexpensive empirical model of IEEE 802.11p radio shadowing in urban environments

General sparse matrix-matrix multiplication (SpGEMM) is a fundamental building block for numerous applications such as algebraic multigrid method, breadth first search and shortest path problem. Compared to other sparse BLAS routines, an efficient parallel SpGEMM algorithm has to handle extra irregularity from three aspects: (1) the number of the nonzero entries in the result sparse matrix is unknown in advance, (2) very expensive parallel insert operations at random positions in the result sparse matrix dominate the execution time, and (3) load balancing must account for sparse data in both input matrices. Recent work on GPU SpGEMM has demonstrated rather good both time and space complexity, but works best for fairly regular matrices. In this work we present a GPU SpGEMM algorithm that particularly focuses on the above three problems. Memory pre-allocation for the result matrix is organized by a hybrid method that saves a large amount of global memory space and efficiently utilizes the very limited on-chip scratchpad memory. Parallel insert operations of the nonzero entries are implemented through the GPU merge path algorithm that is experimentally found to be the fastest GPU merge approach. Load balancing builds on the number of the necessary arithmetic operations on the nonzero entries and is guaranteed in all stages. Compared with the state-of-the-art GPU SpGEMM methods in the CUSPARSE library and the CUSP library and the latest CPU SpGEMM method in the Intel Math Kernel Library, our approach delivers excellent absolute performance and relative speedups on a benchmark suite composed of 23 matrices with diverse sparsity structures.

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An Efficient GPU General Sparse Matrix-Matrix Multiplication for Irregular Data

Graphics processors, or GPUs, have recently been widely used as accelerators in the shared environments such as clusters and clouds. In such shared environments, many kernels are submitted to GPUs from different users, and throughput is an important metric for performance and total ownership cost. Despite the recently improved runtime support for concurrent GPU kernel executions, the GPU can be severely underutilized, resulting in suboptimal throughput. In this paper, we propose Kernelet, a runtime system with dynamic slicing and scheduling techniques to improve the throughput of concurrent kernel executions on the GPU. With slicing, Kernelet divides a GPU kernel into multiple sub-kernels (namely slices). Each slice has tunable occupancy to allow co-scheduling with other slices and to fully utilize the GPU resources. We develop a novel and effective Markov chain based performance model to guide the scheduling decision. Our experimental results demonstrate up to 31.1% and 23.4% performance improvement on NVIDIA Tesla C2050 and GTX680 GPUs, respectively.

Kernelet: High-Throughput GPU Kernel Executions with Dynamic Slicing and Scheduling

Invited Lectures.- Flexible Path Planning Using Corridor Maps.- A Bridging Model for Multi-core Computing.- Contributed Papers.- Robust Kinetic Convex Hulls in 3D.- On Dominance Reporting in 3D.- Stabbing Convex Polygons with a Segment or a Polygon.- An Efficient Algorithm for 2D Euclidean 2-Center with Outliers.- A Near-Tight Bound for the Online Steiner Tree Problem in Graphs of Bounded Asymmetry.- Cache-Oblivious Red-Blue Line Segment Intersection.- The Complexity of Bisectors and Voronoi Diagrams on Realistic Terrains.- Space-Time Tradeoffs for Proximity Searching in Doubling Spaces.- A Scaling Algorithm for the Maximum Node-Capacitated Multiflow Problem.- Linear Time Planarity Testing and Embedding of Strongly Connected Cyclic Level Graphs.- Straight Skeletons of Three-Dimensional Polyhedra.- Randomized Competitive Analysis for Two-Server Problems.- Decompositions and Boundary Coverings of Non-convex Fat Polyhedra.- Approximating Multi-criteria Max-TSP.- An Integer Programming Algorithm for Routing Optimization in IP Networks.- A Constant-Approximate Feasibility Test for Multiprocessor Real-Time Scheduling.- Tight Bounds and a Fast FPT Algorithm for Directed Max-Leaf Spanning Tree.- Engineering Tree Labeling Schemes: A Case Study on Least Common Ancestors.- A Practical Quicksort Algorithm for Graphics Processors.- Bloomier Filters: A Second Look.- Coupled Path Planning, Region Optimization, and Applications in Intensity-Modulated Radiation Therapy.- A New Approach to Exact Crossing Minimization.- A Characterization of 2-Player Mechanisms for Scheduling.- A Local-Search 2-Approximation for 2-Correlation-Clustering.- The Alcuin Number of a Graph.- Time-Dependent SHARC-Routing.- Detecting Regular Visit Patterns.- Improved Approximation Algorithms for Relay Placement.- Selfish Bin Packing.- Improved Randomized Results for That Interval Selection Problem.- Succinct Representations of Arbitrary Graphs.- Edge Coloring and Decompositions of Weighted Graphs.- The Complexity of Sorting with Networks of Stacks and Queues.- Faster Steiner Tree Computation in Polynomial-Space.- Fitting a Step Function to a Point Set.- Faster Swap Edge Computation in Minimum Diameter Spanning Trees.- The Partial Augment-Relabel Algorithm for the Maximum Flow Problem.- An Optimal Dynamic Spanner for Doubling Metric Spaces.- RFQ: Redemptive Fair Queuing.- Range Medians.- Locality and Bounding-Box Quality of Two-Dimensional Space-Filling Curves.- Probabilistic Analysis of Online Bin Coloring Algorithms Via Stochastic Comparison.- On the Complexity of Optimal Hotlink Assignment.- Oblivious Randomized Direct Search for Real-Parameter Optimization.- Path Minima in Incremental Unrooted Trees.- Improved Competitive Performance Bounds for CIOQ Switches.- Two-Stage Robust Network Design with Exponential Scenarios.- An Optimal Incremental Algorithm for Minimizing Lateness with Rejection.- More Robust Hashing: Cuckoo Hashing with a Stash.- Better and Simpler Approximation Algorithms for the Stable Marriage Problem.- Edit Distances and Factorisations of Even Permutations.- Speed Scaling Functions for Flow Time Scheduling Based on Active Job Count.- Facility Location in Dynamic Geometric Data Streams.- The Effects of Local Randomness in the Adversarial Queueing Model.- Parallel Imaging Problem.- An Online Algorithm for Finding the Longest Previous Factors.- Collusion-Resistant Mechanisms with Verification Yielding Optimal Solutions.- Improved BDD Algorithms for the Simulation of Quantum Circuits.- Mobile Route Planning.- How Reliable Are Practical Point-in-Polygon Strategies?.- Fast Divide-and-Conquer Algorithms for Preemptive Scheduling Problems with Controllable Processing Times - A Polymatroid Optimization Approach.- Approximability of Average Completion Time Scheduling on Unrelated Machines.- Relative Convex Hulls in Semi-dynamic Subdivisions.- An Experimental Analysis of Robinson-Foulds Distance Matrix Algorithms.- On the Size of the 3D Visibility Skeleton: Experimental Results.- An Almost Space-Optimal Streaming Algorithm for Coresets in Fixed Dimensions.- Deterministic Sampling Algorithms for Network Design.

Algorithms - ESA 2008 : 16th Annual European Symposium, Karlsruhe, Germany, September 15-17, 2008 : proceedings

A framework for general sparse matrix-matrix multiplication on GPUs and heterogeneous processors

State of the art graphics processors provide high processing power and furthermore, the high programmability of GPUs offered by frameworks like CUDA increases their usability as high-performance coprocessors for general-purpose computing. Sorting is well-investigated in Computer Science in general, but (because of this new field of application for GPUs) there is a demand for high-performance parallel sorting algorithms that fit to the characteristics of modern GPU-architecture.

We present a high-performance in-place implementation of Batcher's bitonic sorting networks for CUDA-enabled GPUs. We adapted bitonic sort for arbitrary input length and assigned compare/exchange-operations to threads in a way that decreases low-performance global-memory access and thereby greatly increases the performance of the implementation.

Fast in-place sorting with CUDA based on bitonic sort

Adaptive bitonic sort is a well known merge-based parallel sorting algorithm. It achieves optimal complexity using a complex tree-like data structure called a bitonic tree. Due to this, using adaptive bitonic sort together with other algorithms usually implies converting bitonic trees to arrays and vice versa. This makes adaptive bitonic sort inappropriate in the context of hybrid sorting algorithms where frequent switches between algorithms are performed. In this article we present a novel optimal sorting algorithm that is based on an approach similar to adaptive bitonic sort. Our approach does not use bitonic trees but uses the input array together with some additional information. Using this approach it is trivial to switch between adaptive bitonic sort and other algorithms. We present an implementation of a hybrid algorithm for GPUs based on bitonic sort and our novel algorithm. This implementation turns out to be the fastest comparison-based sorting algorithm for GPUs found in literature.

A Novel Sorting Algorithm for Many-core Architectures Based on Adaptive Bitonic Sort

State-of-the-art graphics processors provide high processing power and furthermore, the high programmability of GPUs offered by frameworks like CUDA (Compute Unified Device Architecture) increases their usability as high-performance co-processors for general-purpose computing. Sorting is well investigated in Computer Science in general, but (because of this new field of application for GPUs) there is a demand for high-performance parallel sorting algorithms that fit with the characteristics of the modern GPU-architecture. We present a high-performance in-place implementation of Batcher's bitonic sorting networks for CUDA-enabled GPUs. Therefore, we assigned compare/exchange operations to threads in a way that decreases low-performance global-memory access and makes efficient use of high-performance shared memory. This greatly increases the performance of this in-place, comparison-based sorting algorithm. Our implementation outperforms all other algorithms in our tests when sorting 64-bit keys. It is the fastest comparison-based GPU sorting algorithm for 32-bit keys, being only outperformed by (non-comparison-based) radix sort when sorting sequences larger than 223. Copyright © 2011 John Wiley & Sons, Ltd.

Fast in-place, comparison-based sorting with CUDA: a study with bitonic sort

Sorting is a well-investigated topic in Computer Science in general and by now many efficient sorting algorithms for CPUs and GPUs have been developed. There is no swapping, paging, etc. available on GPUs to provide more virtual memory than physically available, thus if one wants to sort sequences that exceed GPU memory using the GPU the problem of external sorting arises.

Parallel external sorting for CUDA-enabled GPUs with load balancing and low transfer overhead

Mobile ad-hoc networks (MANETs) and especially mobile Wireless Sensor Networks (mWSNs) are embedded in the environment and therefore stand under strong influence of its specific characteristics. Beside e.g. sensor input, nodes motion patterns are supposed to be a very basic factor regarding performance. Hence simulations may need to account scenario specific mobility patterns while keeping the tradeoff related to simulation complexity in mind.

This contribution proposes a graph based mobility model, designed to resemble probabilistic node movements according to real world node paths like they may be induced by road grids. The model is presented along with a real world mWSN sample deployment from which the paths are extracted and against which the simulation fine-tuned.

Hagen Peters

Papers

Fast in-place sorting with CUDA based on bitonic sort

A Novel Sorting Algorithm for Many-core Architectures Based on Adaptive Bitonic Sort

Fast in-place, comparison-based sorting with CUDA: a study with bitonic sort

Parallel external sorting for CUDA-enabled GPUs with load balancing and low transfer overhead

Graph-based mobility model for urban areas fueled with real world datasets