Showing papers by "Hai Zhou published in 2018"

SAT-based bit-flipping attack on logic encryptions

Abstract: Logic encryption is a hardware security technique that uses extra key inputs to prevent unauthorized use of a circuit. With the discovery of the SAT-based attack, new encryption techniques such as SARLock and Anti-SAT are proposed, and further combined with traditional logic encryption techniques, to guarantee both high error rates and resilience to the SAT-based attack. In this paper, the SAT-based bit-flipping attack is presented. It first separates the two groups of keys via SAT-based bit-flippings, and then attacks the traditional encryption and the SAT-resilient encryption, by conventional SAT-based attack and by-passing attack, respectively. The experimental results show that the bit-flipping attack successfully returns a circuit with the correct functionality and significantly reduces the execution time compared with other advanced attacks.

Cyclic locking and memristor-based obfuscation against CycSAT and inside foundry attacks

Abstract: The high cost of IC design has made chip protection one of the first priorities of the semiconductor industry. Although there is a common impression that combinational circuits must be designed without any cycles, circuits with cycles can be combinational as well. Such cyclic circuits can be used to reliably lock ICs. Moreover, since memristor is compatible with CMOS structure, it is possible to efficiently obfuscate cyclic circuits using polymorphic memristor-CMOS gates. In this case, the layouts of the circuits with different functionalities look exactly identical, making it impossible even for an inside foundry attacker to distinguish the defined functionality of an IC by looking at its layout. In this paper, we propose a comprehensive chip protection method based on cyclic locking and polymorphic memristor-CMOS obfuscation. The robustness against state-of-the-art key-pruning attacks is demonstrated and the overhead of the polymorphic gates is investigated.

A comparative investigation of approximate attacks on logic encryptions

Abstract: Logic encryption is an important hardware protection technique that adds extra keys to lock a given circuit. With recent discovery of the effective SAT-based attack, new enhancement methods such as SARLock and Anti-SAT have been proposed to thwart the SAT-based and similar exact attacks. Since these new techniques all have very low error rate, approximate attacks such as Double DIP and AppSAT have been proposed to find an almost correct key with low error rate. However, measuring the performance of an approximate attack is extremely challenging, since exact computation of the error rate is very expensive, while estimation based on random sampling has low confidence. In this paper, we develop a suite of scientific encryption benchmarks where a wide range of error rates are possible and the error rate can be found out by simple eyeballing. Then, we conduct a thorough comparative study on different approximate attacks, including AppSAT and Double DIP. The results show that approximate attacks are far away from closing the gap and more investigations are needed in this area.

An Efficient Non-Gaussian Sampling Method for High Sigma SRAM Yield Analysis

Abstract: Yield1 analysis of SRAM is a challenging issue, because the failure rates of SRAM cells are extremely small. In this article, an efficient non-Gaussian sampling method of cross entropy optimization is proposed for estimating the high sigma SRAM yield. Instead of sampling with the Gaussian distribution in existing methods, a non-Gaussian distribution, i.e., a joint one-dimensional generalized Pareto distribution and (n-1)-dimensional Gaussian distribution, is taken as the function family of practical distribution, which is proved to be more suitable to fit the ideal distribution in the view of extreme failure event. To minimize the cross entropy between practical and ideal distributions, a sequential quadratic programing solver with multiple starting points strategy is applied for calculating the optimal parameters of practical distributions. Experimental results show that the proposed non-Gaussian sampling is a 2.2--4.1× speedup over the Gaussian sampling, on the whole, it is about a 1.6--2.3× speedup over state-of-the-art methods with low- and high-dimensional cases without loss of accuracy

Multiobjectivism in Dark Silicon Age

Abstract: MCSoCs, with their scalability and parallel computation power, provide an ideal implementation base for modern embedded systems. However, chip designers are facing a design challenge wherein shrinking component sizes though have improved density but started stressing energy budget. This phenomenon, that is called utilization wall, has revolutionized the semiconductor industry by shifting the main purpose of chip design from a performance-driven approach to a complex multiobjective one. The area of the chip which cannot be powered is known as dark silicon. In this chapter, we address the multiobjectivism in dark silicon age. First, we overview state-of-the-art works in a categorized manner. Second, we introduce a NoC-based MCSoC architecture, named shift sprinting, in order to increase overall reliability as well as gain high performance. Third, we explain an application mapping approach, called round rotary mapping, for HWNoC-based MCSoC in order to first balance the usage of wireless links by avoiding congestion over wireless routers and second spread temperature across the whole chip by utilizing dark silicon. Finally, we conclude the chapter by providing a future outlook of dark silicon research trend.

Design and Synthesis of Self-Healing Memristive Circuits for Timing Resilient Processor Design

Abstract: Modern microprocessors suffer from significant on-chip variation at the advanced technology nodes. The development of CMOS-compatible memristive devices has brought nonvolatile capability into silicon technology. This paper explores new applications for memristive devices to resolve performance degradations that result from process variation. Novel self-healing flip-flop and clock buffers are developed to automatically detect timing violation and to perform timing recovery by tuning the resistance values of memristor devices. To incorporate the circuit techniques into VLSI circuits design, novel device placement and tuning algorithms have been developed. The proposed design methodology is demonstrated in a 45-nm fast Fourier transform processor design. Our test results show that performance gains of up to 20% can be achieved using the proposed self-healing circuits, with only 1% area

Cut Redistribution and Insertion for Advanced 1-D Layout Design via Network Flow Optimization

Abstract: Given a 1-D layout with horizontal wires, cut redistribution technique is used for sliding the line-end cuts in order to merge them vertically or resolve spacing conflicts. A pair of movable cuts could have three possible relations, left-of, right-of, and merge-into. We observe that if the left-right-merge orderings of cuts are fixed, the cut redistribution can be formulated as a network flow problem, which can be solved efficiently. We also find that inserting cuts can resolve the spacing conflicts in some circumstances. According to the observations, we proposed a network-flow-based cut redistribution and insertion method for 1-D layout design. First, the orderings of the cuts are generated according to a predefined distribution. The hyperparameters of the distribution are tuned with Bayesian optimization. In order to resolve the conflicts, the cuts are redistributed and extra cuts are also inserted with network-flow-based method. Afterward, we adopt the complementary e-beam lithography to eliminate the unresolved conflicts. Finally, two wire length reduction techniques have been proposed for two different processes of e-beam, respectively. Experimental results show that compared with the existing integer linear programming-based method that does not consider the cut insertion, our method can achieve $132\times $ speedup and higher quality.

R-Accelerator: A Reconfigurable Accelerator with RRAM Based Logic Contraction and Resource Optimization for Application Specific Computing

Abstract: In this paper, we introduce a novel reconfigurable accelerator (R-accelerator) design which embeds RRAM device into traditional logic circuits for high-performance application specific computing. To facilitate the synthesis of the proposed RRAM based logic cell, a special logic contraction technique is developed to maximize the area saving. In order to optimize the arithmetic unit array for instruction set mapping and interconnect routing, a new resource allocation algorithm is also proposed to achieve further saving in area and power. Using a fully integrated design flow with commercial design tools, our experimental results show that the proposed RRAM based R-accelerator architecture offers 45% area improvement, 33% power reduction and 32% performance enhancement in a 45nm CMOS process compared with conventional CMOS design.

A RRAM-based Coarse Grain Reconfigurable Array for Neural Network Accelerators

Abstract: We propose a novel RRAM-based coarse grain reconfigurable array design for neural network computing. The proposed reconfigurable array design consists of RRAM-based reconfigurable AU array and the associated interconnects using novel RRAM-based multiplexer logic. A significant area saving is achieved compared with conventional design due to the simplification of logic expression as well as the saving of storage space and routing congestions from conventional switch controller. The experiments using 45nm CMOS technology show 47% area improvement and 27% performance enhancement can be achieved by using proposed RRAM-based reconfigure array technique.