For high power voltage source converter based high voltage direct current transmission systems, modular multilevel converter (MMC) is the most popular circuit topology nowadays. It is known that the existence of the second-order harmonic circulating current (SHCC) component in the arm current of MMC increases the loss of the converter. Conventionally, the SHCC component eliminating methods are usually adopted to reduce the loss. The relationship between the loss of MMC and the SHCC component is analyzed first in this paper. The analysis shows that the conventional eliminating methods are not optimal in terms of the minimum loss of MMC. A loss optimization control scheme is also proposed by injecting the optimal SHCC component into the arm current of MMC, rather than eliminating the SHCC component of the arm current. The simulation and experimental results of the ±350 kV/1000 MW MMC and the down-scaled MMC setup verify the correctness and effectiveness of the proposed loss optimization method under different operation conditions.

Loss Optimization of MMC by Second-Order Harmonic Circulating Current Injection

This article proposes a mission profile-based reliability prediction method for modular multilevel converters (MMCs). It includes key modeling steps, such as long-term mission profile, analytical power loss models, system-level and component-level thermal modeling, lifetime modeling, Monte Carlo analysis, and redundancy analysis. Thermal couplings and uneven thermal stresses among submodules are considered. A case study of a 15-kVA down-scale MMC has been used to demonstrate the proposed method and validate the theoretical analysis. The outcomes serve as a first step for developing realistic reliability analysis and model-based design methods for full-scale MMCs in practical applications.

Mission Profile-Based System-Level Reliability Prediction Method for Modular Multilevel Converters

As one of the most vulnerable components to temperature and temperature cycling conditions in power electronics converter systems in these application fields as wind power, electric vehicles, drive system, etc., power semiconductor devices draw great concern in terms of reliability. Owing to the wide utilization of power semiconductor devices in various power applications, especially insulated gate bipolar transistors (IGBTs), power semiconductor devices have been studied extensively regarding increasing reliability methods. This study comparatively reviews recent advances in the area of reliability research for power semiconductor devices, including condition monitoring (CM), active thermal control (ATC), and remaining useful lifetime (RUL) estimation techniques. Different from previous review studies, this technical review is carried out with the aim of providing a comprehensive overview of the correlation between various enhancing reliability techniques and discussing the corresponding merits and demerits by using 144 related up-to-date papers. The structure and failure mechanism of power semiconductor devices are first investigated. Different failure indicators and recent associated CM techniques are then compared. The ATC approaches following the type of converter systems are further summarized. Furthermore, RUL estimation techniques are surveyed. This paper concludes with summarized challenges for future research opportunities regarding reliability improvement.

Enhance Reliability of Semiconductor Devices in Power Converters

This paper deals with the blocking of DC-fault current during DC cable short-circuit conditions in HVDC (High-Voltage DC) transmission systems utilizing Modular Multilevel Converters (MMCs), where a new SubModule (SM) topology circuit for the MMC is proposed. In this SM circuit, an additional Insulated-Gate Bipolar Translator (IGBT) is required to be connected at the output terminal of a conventional SM with a half-bridge structure, hereafter referred to as HBSM, where the anti-parallel diodes of additional IGBTs are used to block current from the grid to the DC-link side. Compared with the existing MMCs based on full-bridge (FB) SMs, the hybrid topologies of HBSM and FBSM, and the clamp-double SMs, the proposed topology offers a lower cost and lower power loss while the fault current blocking capability in the DC short-circuit conditions is still provided. The effectiveness of the proposed topology has been validated by simulation results obtained from a 300-kV 300-MW HVDC transmission system and experimental results from a down-scaled HVDC system in the laboratory.

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Protection of the MMCs of HVDC Transmission Systems against DC Short-Circuit Faults

Due to the parameter mismatch, the unbalanced power loss distribution among SMs in the modular multilevel converter (MMC) can be introduced and further deteriorated by the low-frequency asynchronous switching transients related to no-carrier modulation techniques. The unbalanced thermal stress can reduce the reliability of the MMC and increase the complexity of cooling system design. Nevertheless, an internal balance mechanism exists in the MMC thanks to the capacitor voltage balancing. It contributes to an even conduction loss dissipation among SMs, which is studied and revealed in this paper. Moreover, a computationally light conduction loss estimation method is proposed correspondingly relying on the characteristics of semiconductors and the arm current only. Simulations and experiments are conducted to verify the effectiveness the proposed method.

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Balanced Conduction Loss Distribution among SMs in Modular Multilevel Converters

The power loss of the controllable switches in modular multilevel converter (MMC) HVDC transmission systems is an important factor, which can determine the design of the operating junction temperatures. Due to the dc current component, the approximate calculation tool provided by the manufacturer of the switches cannot be used for the losses of the switches in the MMC. Based on the enabled probabilities of each SM in an arm, the current analytical models of the switches can be determined. The average and RMS currents can be obtained from the corresponding current analytical model. Then, the conduction losses can be calculated, and the switching losses of the switches can be estimated according to the upper limit of the switching frequency. Finally, the thermal resistance model of the switches can be utilized, and the junction temperatures can be estimated. A comparison between the calculation and PSCAD simulation results shows that the proposed method is effective for estimating the junction temperatures of the switches in the MMC.

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Haitian Wang

Papers

Power Loss and Junction Temperature Analysis in the Modular Multilevel Converters for HVDC Transmission Systems