A low temporal noise and high dynamic range CMOS image sensor is developed. A 1Mpixel CMOS image sensor with column-parallel folding-integration and cyclic ADCs has 80μVrms (1.2e-) temporal noise, 82 dB dynamic range using 64 samplings in the folding-integration ADC mode. Very high variable gray-scale resolution of 13b through 19b is attained by changing the number of samplings of pixel outputs. The implemented CMOS image sensor using a 0.18-μm technology has the sensitivity of 10-V/lx·s, the conversion gain of 67- μV/e-, and linear digital code range of more than 4 decades.

A Low-Noise High Intrascene Dynamic Range CMOS Image Sensor With a 13 to 19b Variable-Resolution Column-Parallel Folding-Integration/Cyclic ADC

Systems, methods and devices for reducing noise in health monitoring including monitoring systems, methods and/or devices receiving a health signal and/or having at least one electrode or sensor for health monitoring.

Health monitoring systems and methods

For low-light-level imaging, the performance of a CMOS image sensor (CIS) is usually limited by the temporal readout noise (TRN) generated from its analog readout circuit chain. Although a sub-electron TRN level can be achieved with a high-gain pixel-level amplifier, the pixel uniformity is highly impaired up to a few percent by its open-loop amplifier structure [1]. The TRN can be suppressed without this penalty by employing either a high-gain column-level amplifier [2] or a correlated multiple sampling (CMS) technique [3–5]. However, only 1-to-2 electron TRN level has been reported with the individual use of these approaches [2–5], and the low-frequency noise of the in-pixel source follower i.e. 1/fand RTS noise is a further limitation. Therefore, by implementing a high-gain column-level amplifier and CMS technique together with an in-pixel buried-channel source follower (BSF) [6], the TRN level can be reduced even further.

A 0.7e − rms -temporal-readout-noise CMOS image sensor for low-light-level imaging

There is provided a solid-state imaging device capable of correcting a blackening phenomenon caused by intense light, with a small-scale circuit configuration An AD converter 130 that performs sampling of an output voltage VS on a column signal line 111 includes a comparator 131 that compares the output voltage VS with a ramp-wave reference voltage during a sampling period; a judging circuit 132 that accepts as input an output from the comparator 131 and judges a voltage level of the output voltage VS; and a memory portion 133 that stores, as a digital value, a count value corresponding to the output voltage VS, based on an output from the judging circuit 132 The comparator 131 amplifies a voltage change of the output voltage VS obtained after a lapse of a reset period in which a voltage of a FD portion 103 in a pixel circuit 100 is reset, and the judging circuit 132 judges, based on the voltage change, whether light received by the pixel circuit 100 is intense light, during a predetermined detection period between the reset period and a period in which an output voltage Vrst obtained after the reset is sampled

Solid-state imaging device

This paper presents a low-power always-on image sensor for mobile and wearable device applications. The sensor continuously captures images for smart sensing, such as face detection, eye tracking, and gesture recognition, and it provides high-resolution images for capturing pictures with a unified sensor. The sensor employs a switchable dual mode: always-on (AO) mode with low power consumption and photo-shooting (PS) mode with high signal-to-noise ratio. For dual-mode operation with high energy efficiency, we implemented dynamic voltage scaling that provides 0.9 V analog–digital supply voltage for the AO mode and 3.3 V analog–1.8 V digital supply voltage for the PS mode. For low-voltage operation in the AO mode, a conventional four-transistor pixel operates as a charge-shared pixel. In order to suppress power consumption and frequency in conventional single-slope analog-to-digital converters (ADC), two neighboring column-parallel ADCs are reconfigured to one successive-approximation ADC for low-voltage and low-frequency operation in the AO mode with negligible area overhead. The fabricated 640 $\,\times\,$ 480 pixel prototype sensor operates at 45.5 $\mu$ W (at 15 fps, 320 $\,\times\,$ 240) in the AO mode, which significantly extends battery life when performing always-on sensing.

Always-On CMOS Image Sensor for Mobile and Wearable Devices

The noise performance of CMOS image sensors has improved significantly. The most popular way to reduce readout circuit noise is amplifying pixel output using a preamplifier at the foremost stage of readout chain to suppress the noise of following readout chains in high analog gain [1–3]. Another approach is multiple sampling which can reduce temporal noise of pixel and readout circuit by sampling the same pixel repeatedly and processing (generally averaging) the sampled data [4, 5]. However, both approaches require additional circuitry in the column readout chain which requires extra silicon area and power consumption. Furthermore, it is hard to implement a decent per-column amplifier in a small pixel pitch sensor, such as 1.4µm pixel, because of narrow layout space. In addition, the second approach requires longer readout time proportional to the number of samples. This paper presents a cost-effective low noise CMOS image sensor readout chain using pseudo-multiple sampling technique.

A 1.1e- temporal noise 1/3.2-inch 8Mpixel CMOS image sensor using pseudo-multiple sampling

An image sensor includes a sampling circuit, which is responsive to ramp and input signals provided by a pixel array. The sampling circuit is configured to perform a correlated double sampling (CDS) operation on a reset component of the input signal and an image component of the input signal. A reset circuit is also provided, which is configured to reset an output signal generated by the sampling circuit to a first level in response to a reset control signal. This reset control signal can be active during at least one of a first reset interval and a second reset interval. The first reset interval precedes a first comparison interval during which a first comparison operation is performed on the ramp signal and the reset component. The second reset interval precedes a second comparison interval during which a second comparison operation is performed on the ramp signal and the image component.

Correlated double sampling circuit, analog to digital converter and image sensor including the same

A CDS circuit includes first capacitors; second capacitors; and a switch arrangement which, in response to a switch control signal, connects the first capacitors in series between a pixel signal output node and a ground to compress the pixel signal and connects the second capacitors in series between a ramp signal output node and the ground to compress the ramp signal, or connects the first capacitors in parallel between the pixel signal output node and a first input node of the comparator and connects the second capacitors in parallel between the ramp signal output node and a second input node of the comparator.

Correlated double sampling circuit, method thereof and devices having the same

A correlated double sampling (CDS) circuit may include a sampling circuit and a switching circuit. The CDS circuit may perform a CDS operation on a reset component of an input signal and an image component of the input signal based on a ramp signal, and the CDS circuit may generate an output signal. The switching circuit may include an auto-zero switch that connects a first input terminal receiving the input signal to an output node in response to an auto-zero control signal during an auto-zero interval. The switching circuit may connect a first terminal of the auto-zero switch to a reference voltage in order to cutoff a leakage current flowing to the auto-zero switch in response to a first boosting control signal during a first comparison interval and a second comparison interval. The output signal may be provided at the output node.

Correlated double sampling circuit and image sensor including the same

An analog-to-digital converter including a comparator configured to compare a pixel signal received at a first input terminal of the comparator with a ramp signal received at a second input terminal of the comparator and generate a comparison signal as a result of the comparison; and a ramp signal supply circuit configured to provide the ramp signal to the comparator, wherein the ramp signal supply circuit generates a first signal as part of the ramp signal in response to the comparison signal and a first clock signal being received at the ramp signal supply circuit, wherein a slope of the first signal sequentially changes until the comparison signal makes a transition from one logic level to another and, after the transition, the ramp signal supply circuit generates a second signal as part of the ramp signal, wherein a slope of the second signal sequentially changes, wherein the slope of the second signal is opposite the slope of the first signal.

Han Yang

Papers

A 1.1e- temporal noise 1/3.2-inch 8Mpixel CMOS image sensor using pseudo-multiple sampling

Correlated double sampling circuit, analog to digital converter and image sensor including the same

Correlated double sampling circuit, method thereof and devices having the same

Correlated double sampling circuit and image sensor including the same

Analog-to-digital converter and devices including the same