Physics of semiconductor devices / S.M. Sze

Electro-Static Discharge (ESD) is critical for the reliability of integrated circuits. Applying ESD model in circuit simulation could help to predict and avoid potential failure caused by ESD. This paper proposes a SPICE macro model for parasitic NPN ESD and related methods for extracting SPICE model parameters. The macro model utilizes the Taylor series to express collector current of NPN transistor under avalanche breakdown, and thus solves the problem of lack of convergence in prior models. The macro model’s parameters are obtained by device measurement together with curve fitting. A device with parasitic NPN was fabricated in SMIC with 0.18um BCD process to verify the macro model. Chip tests indicate that the simulation results of the device’s macro model exactly match with the real ESD characteristics of the device, which demonstrate the validity of the macro model for parasitic NPN ESD behavior in circuit simulations. Introduction ESD (Electro-Static Discharge) is a serious threat to the reliability and yield of integrated circuits. ESD stress currents flowing into internal circuits may cause unrecoverable damage, so it is necessary to provide ESD protection to integrated circuits [1-6]. At present, ESD stress tests are performed during trial manufacture. If these tests are failed, a conventional approach to response is investigating the cause of the ESD damage and reexamining the design rule and process conditions. Such approach leads to high expense and time waste. Therefore, it is important to predict ESD behavior, potential failure and test damage resistance before trail manufacture. Performing ESD simulation to protection circuits during circuit design and layout is an effective approach for solving the foregoing problem [7, 8]. This paper presents a SPICE macro model for NPN ESD. The SPICE model parameters are extracted based on ESD device measurement. The macro model is verified by experimental data which demonstrates the validity of the macro model for NPN devices in ESD circuit simulations. An Equivalent Circuit for a Parasitic NPN ESD Fig. 1(a) shows a cross-sectional diagram of a typical parasitic NPN ESD in a BCD process, Fig. 1(b) shows an equivalent circuit of the parasitic NPN ESD, comprising an NPN transistor Q1 and some parasitic elements. Dnws refers to the parasitic diode between the N-well and P-substrate. Rsub refers to the parasitic resistor in the P-substrate. Rbase refers to a total base resistance, equaling to a sum of resistances of the Pbase resistor and contact resistor. Rc and Re respectively refer to the parasitic resistor of collector and the parasitic resistor of emitter. The on-resistance Ron in the high current linear region after device snapback is approximately complied to the following equation, Ron=Rc+Re. Iaval refers to a controlled current source to represent the hole injection current when the C-B junction is under avalanche breakdown region. 6th International Conference on Information Engineering for Mechanics and Materials (ICIMM 2016) © 2016. The authors Published by Atlantis Press 413 c aval I M I ) 1 ( − = (1) (a) Cross section (b) its equivalent circuit Fig. 1. A typical Parasitic NPN ESD Where M is the avalanche multiplication factor [9] n cb cb BV V M ) / ( 1 1 − = (2) Vcb refers to a biased voltage on the C-B junction and BVcb represents a breakdown voltage of C-B junction. Avalanche Multiplication Directly applying formula (1) or (2) into prior SPICE simulators returns an incorrect result indicating that a snapback phenomenon emerges. The reason is that when Vcb BVcb, and M∝, the simulating result is lack of convergence. Thus an adjustment to formula (1) is necessary for obtaining a convergent result of SPICE simulation. ) exp(m M = (3) Wherein ) ) ( 1 ln( ) ) ( 1 1 ln( n cb cb n cb cb BV V BV V m − − = − = (4) According to the Taylor series 2 3 ln(1 ) 2 3 x x x x − = − − − − for 1 < x (5) The m could be expressed as 2 3 1 1 1 2 3 n n n xn

/pdf/modeling-and-simulation-of-parasitic-npn-esd-38j81tq9r4.pdf

Modeling and Simulation of Parasitic NPN ESD

In this paper, a low-capacitance silicon-controlled rectifier (LCSCR) structure with high-CDM robustness are proposed for high-speed I/O ESD protection. The LCSCR implemented with TSMC 4nm bulk FinFET technology can achieve high ESD robustness $(\gt 9\mathrm{A})$, low capacitance $(\lt 120$ fF) and low dynamic on-resistance $(\lt 0.5$ ohm) with compact geometry.

Hanfei Yang

Papers

Modeling and Simulation of Parasitic NPN ESD

Low-Capacitance, High-CDM ESD Protection Design with FEOL and BEOL Co-Optimization in 4nm Bulk FinFET Technology