https://cyberleninka.org/article/n/1380904.pdf

ASAP7: A 7-nm finFET predictive process design kit

Bottom-up nanofabrication by area-selective atomic layer deposition (ALD) is currently gaining momentum in semiconductor processing, because of the increasing need for eliminating the edge placement errors of top-down processing. Moreover, area-selective ALD offers new opportunities in many other areas such as the synthesis of catalysts with atomic-level control. This Perspective provides an overview of the current developments in the field of area-selective ALD, discusses the challenge of achieving a high selectivity, and provides a vision for how area-selective ALD processes can be improved. A general cause for the loss of selectivity during deposition is that the character of surfaces on which no deposition should take place changes when it is exposed to the ALD chemistry. A solution is to implement correction steps during ALD involving for example surface functionalization or selective etching. This leads to the development of advanced ALD cycles by combining conventional two-step ALD cycles with correction steps in multistep cycle and/or supercycle recipes.

From the Bottom-Up: Toward Area-Selective Atomic Layer Deposition with High Selectivity.

Area-selective atomic layer deposition (ALD) is rapidly gaining interest because of its potential application in self-aligned fabrication schemes for next-generation nanoelectronics. Here, we introduce an approach for area-selective ALD that relies on the use of chemoselective inhibitor molecules in a three-step (ABC-type) ALD cycle. A process for area-selective ALD of SiO2 was developed comprising acetylacetone inhibitor (step A), bis(diethylamino)silane precursor (step B), and O2 plasma reactant (step C) pulses. Our results show that this process allows for selective deposition of SiO2 on GeO2, SiNx, SiO2, and WO3, in the presence of Al2O3, TiO2, and HfO2 surfaces. In situ Fourier transform infrared spectroscopy experiments and density functional theory calculations underline that the selectivity of the approach stems from the chemoselective adsorption of the inhibitor. The selectivity between different oxide starting surfaces and the compatibility with plasma-assisted or ozone-based ALD are distinct features of this approach. Furthermore, the approach offers the opportunity of tuning the substrate-selectivity by proper selection of inhibitor molecules.

Area-Selective Atomic Layer Deposition of SiO2 Using Acetylacetone as a Chemoselective Inhibitor in an ABC-Type Cycle

Continuous rapid shrinking of feature size made the authorities to seek alternative patterning methods as the conventional photolithography comes with its intrinsic resolution limit. In this regard, some promising techniques have been proposed as next-generation lithography (NGL) that has the potentials to achieve both high-volume production and very high resolution. This article reviews the promising NGL techniques and introduces the challenges and a perspective on future directions of the NGL techniques. Extreme ultraviolet lithography (EUVL) is considered as the main candidate for sub-10-nm manufacturing, and it could potentially meet the current requirements of the industry. Remarkable progress in EUVL has been made and the tools will be available for commercial operation soon. Maskless lithography techniques are used for patterning in R&D, mask/mold fabrication and low-volume chip design. Directed self-assembly has already been realized in laboratory and further effort will be needed to make it as NGL solution. Nanoimprint lithography has emerged attractively due to its simple process steps, high throughput, high resolution and low cost and become one of the commercial platforms for nanofabrication. However, a number of challenging issues are waiting ahead, and further technological progresses are required to make the techniques significant and reliable to meet the current demand. Finally, a comparative study is presented among these techniques.

/pdf/promising-lithography-techniques-for-next-generation-logic-1bbzk3irp4.pdf

Promising lithography techniques for next generation logic devices : a review

When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today’s 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy. A focus has been on methodologies, challenges, and difficulties when ITRS approaches the end. The discussions extend to new channel materials beyond the Moore era.

Miniaturization of CMOS.

In this paper we discuss edge placement error (EPE) for multi-patterning application and compare the EPE budget with the one for EUV single expose application case. These two patterning methods are candidate for the manufacturing of 10-nm and 7-nm logic semiconductor devices. EUV will enable 2D random pattern layout, while in the multi-patterning case a more restricted 1D design layout is needed. For the 1D design approach we discuss the patterning control spacer pitch division resulting in complex multi-layer alignment and EPE optimization strategies. Solutions include overlay and CD metrology based on angle resolved scatterometry, scanner actuator control to enable high order overlay corrections and computational lithography optimization to minimize imaging induced pattern placement errors of devices and metrology targets. We use 10-nm node experimental data and extrapolate the error budgets towards the 7-nm technology node. The experimental data will be based on NXE:3300B and NXT:1960Bi/NXT:1970Ci exposure systems. The results are compared to the more straightforward alternative of using single expose patterning with EUV for all critical layers.

Overlay and edge placement control strategies for the 7nm node using EUV and ArF lithography

EUV lithography is expected to be introduced in volume manufacturing at the 10-nm and 7-nm node. Especially in these first EUV nodes, critical layer patterning will be balanced with the use of ArF immersion. As a consequence a good overlay and placement matching between both lithography methods becomes an enabling factor for EUV. In this paper we present an integral method to optimize critical layer patterning across the EUV and ArF scanner platform, such that good overlay and device pattern placement is achieved. It is discussed that besides classical overlay control methods, also the optimization of the ArF and EUV imaging steps is needed. Best matching is achieved by applying high-order field-to-field overlay corrections for both imaging and overlay. The lithography architecture we build for these higher order corrections connects the dynamic scanner actuators with the angle resolved scatterometer via a separate computational application server. Improvements of CD uniformity are based on source mask optimization for EUV combined with CD optimization using freeform intra-field dose actuator in the immersion scanner.

Hannah Wei

Papers

Overlay and edge placement control strategies for the 7nm node using EUV and ArF lithography

Across scanner platform optimization to enable EUV lithography at the 10-nm logic node