Showing papers by "Hans Norström published in 2002"
Patent•
29 Apr 2002
TL;DR: In this paper, an IC fabrication method consisting of providing a substrate (10, 41), forming an active region (41) for a bipolar transistor and a MOS device in the substrate, forming isolation areas (81) around, in a horizontal plane, the active regions, forming a gate region (111, 112) on the active region for the bipolar transistor, and forming a layer (141) of an insulating material on the MOS gate region and on the transistor for the transistor.
Abstract: The present invention refers to an IC fabrication method comprising: providing a substrate (10, 41); forming an active region (41) for a bipolar transistor and an active region (41) for a MOS device in the substrate (10); forming isolation areas (81) around, in a horizontal plane, the active regions; forming a MOS gate region (111, 112) on the active region for the MOS device; forming a layer (141) of an insulating material on the MOS gate region and on the active region (31) for the transistor; and defining a base region in the active region for the transistor by producing an opening (143) in the insulating layer (141) such that the remaining portions of the insulating layer (141) partly cover the active region for the bipolar transistor. The insulating layer (141) remains on the MOS gate region to encapsulate and protect the MOS gate region during subsequent manufacturing steps.
55 citations
Patent•
10 Apr 2002
TL;DR: In this paper, a method for forming shallow and deep trenches for isolation of semiconductor devices comprised in a circuit, comprising providing a semiconductor substrate, optionally forming a first dielectric layer on said substrate, forming at least one shallow trench by using a first mask, said shallow trench extending into said substrate; forming a second dielectrics layer of a predetermined thickness on the structure obtained subsequent to the step of forming a shallow trench; and forming a deep trench in said opening, said deep trench extending further into the substrate and being self-aligned to the shallow trench.
Abstract: In the fabrication of an integrated circuit, particularly an integrated circuit for radio frequency applications, a method for forming shallow and deep . trenches for isolation of semiconductor devices comprised in said circuit, comprising providing a semiconductor substrate; optionally forming a first dielectric layer on said substrate; forming at least one shallow trench by using a first mask, said shallow trench extending into said substrate; forming a second dielectric layer of a predetermined thickness on the structure obtained subsequent to the step of forming at least one shallow trench; forming at least one opening in said second dielectric layer by using a second mask with an edge of said second mask aligned to an edge of said shallow trench with a maximum misalignment of half the predetermined thickness, said opening extending within the shallow trench to the bottom thereof, whereby a spacer of a width equal to the predetermined thickness is formed in said shallow trench and along said edge thereof; and forming a deep trench in said opening by using said second dielectric layer as a hard mask, said deep trench extending further into said substrate and being self-aligned to said shallow trench.
3 citations
Patent•
15 Oct 2002
TL;DR: A lateral pnp transistor as mentioned in this paper comprises a p-type doped semiconductor substrate (10, 41) and a PMOS transistor structure including an n-doped region (41), an ndoped gate region (111, 194), and a buried n+ type doped region(31) located underneath the n-Doped region.
Abstract: A lateral pnp transistor device comprises a p-type doped semiconductor substrate (10, 41) and a PMOS transistor structure including an n-doped region (41); an n-doped gate region (111, 194) and p-doped source (198) and drain (199) regions; and a buried n+-type doped region (31) located underneath the n-doped region (41). According to the invention the source region is shortened to the gate region and constitutes an emitter of the pnp transistor device; the drain region constitutes a collector of the pnp device; and the n-type doped region constitutes a base of the pnp device. The device includes also a buried p-type doped channel (506) formed in the n-doped region (41), which interconnects the source (198) and drain (199) regions to increase the beta value of the device. The transistor may further comprise a single contact (603) interconnecting the source (198) and gate (194) regions in a self-aligned manner.
1 citations
Patent•
15 Oct 2002
TL;DR: In this article, a procede de fabrication consistant a mettre en oeuvre un substrat en silicium a dopage de type p (10) comportant une region de surface dopee n+ (31) en tant que sous-collecteur, a deposer dessus, par epitaxie, une couche de silicia, comprenant du germanium et un dopant de type n, mais separe de la region collectrice, a former dans les couches epitaxiales (41
Abstract: L'invention concerne, dans le cadre du deroulement de fabrication de transistors semi-conducteurs mesa en silicium-germanium, un procede de fabrication consistant a mettre en oeuvre un substrat en silicium a dopage de type p (10) comportant une region de surface dopee n+ (31) en tant que sous-collecteur, a deposer dessus, par epitaxie une couche de silicium (41) comprenant un dopant de type n, puis a deposer dessus, par epitaxie, une couche de silicium (174) comprenant du germanium et un dopant de type p, a former, dans les couches epitaxiales (41, 174), des zones de champ isolees (81) autour, dans un plan horizontal, d'une partie des couches epitaxiales (41, 174) afin de definir simultanement une region collectrice a dopage de type n (41) sur le sous-collecteur (31), dessus, une region de base a dopage de type p (174), et un connecteur de collecteur a dopage de type n sur le sous-collecteur (31), mais separe de la region collectrice a dopage de type n (41) et de la region de base a dopage de type p (174), et a former dans la region de base a dopage de type p (174) une region emettrice a dopage de type n.