FPGA packing and placement without routability consideration could lead to unroutable results for high-utilization designs. Conventional FPGA packing and placement approaches are shown to have severe difficulties to yield good routability. In this paper, we propose a FPGA packing and placement engine called UTPlaceF that simultaneously optimizes wirelength and routability. A novel physical and congestion aware packing algorithm and several congestion aware detailed placement techniques are proposed. Compared with the top 3 winners of ISPD'16 FPGA placement contest, UTPlaceF can achieve 3.3%, 7.7% and 28.3% better routed wirelength with similar or shorter runtime.

UTPlaceF: a routability-driven FPGA placer with physical and congestion aware packing

Field programmable gate array (FPGA) packing and placement without routability consideration could lead to unroutable results for high-utilization designs. Conventional FPGA packing and placement approaches are shown to have severe difficulties to yield good routability. In this paper, we propose an FPGA packing and placement engine called UTPlaceF that simultaneously optimizes wirelength and routability. A novel physical and congestion aware packing algorithm and a hierarchical detailed placement technique are proposed. UTPlaceF outperforms state-of-the-art FPGA placers simultaneously in runtime and solution quality on International Symposium on Physical Design (ISPD) 2016 benchmark suite. Compared with the top three winners of ISPD’16 FPGA placement contest, UTPlaceF can deliver 6.2%, 11.6%, and 29.1% better routed wirelength with shorter runtime.

UTPlaceF: A Routability-Driven FPGA Placer With Physical and Congestion Aware Packing

steps intheFPGAdesign flow - technology mapping into LUTs Bothtechnology mapping andcircuit clustering have alarge impact andLUTnetlist clustering. onFPGAdesigns interms ofcircuit performance, area, andpower ForLUT-based FPGAs, technology mapping converts agiven dissipation. Existing FPGAdesign flows carry outthese two Boolean circuit into afunctionally equivalent network comprised synthesis steps sequentially. Sucha two-step approach cannot only ofLUTs.Itisanimportant synthesis step forFPGAdesign guarantee that thefinal delay ofthecircuit isoptimal, because the flowbecause itdirectly defines thenumber ofLUTsusedforthe quality ofclustering depends significantly ontheinitial mapping design andthecritical pathlength passing through these LUTs. result. Toaddress this problem, wedevelop analgorithm that There aremanytechnology mapping algorithms published inthe performs mapping andclustering simultaneously andoptimallyliterature toimprove mapping depth/delay [7][9][16][18][2 5],

http://ieeexplore.ieee.org/iel5/11109/35624/01688844.pdf

Optimal Simultaneous Mapping andClustering forFPGADelay Optimization

Applications targeting FPGA integrated systems impose strict energy, channel width and delay constraints. We introduce the first many-objective clustering, MO-Pack, that targets these performance metrics concurrently. Detailed performance comparisons over state of the art clustering strategies targeting energy (P-T-VPack), delay (T-VPack), channel width (iRAC), and timing and routability (T-RPack) show that MO-Pack achieves its goals without increasing the logic area.

MO-pack: many-objective clustering for FPGA CAD

Cluster-based logic blocks from most commercial FPGA products do not have an input bandwidth constraint, i.e., limiting the number of signals going from routing channels into the block. We show that high quality packing for such logic blocks can be easily achieved based on k-way partitioning. We implemented 2 such packing tools: PPack (routability-only) and its timing driven version TPPack. Experimental results show that they have superior quality. Compared to T-VPack, PPack reduces total wire-length and minimal channel width by 22.6% and 22.6% with a 1.9% performance gain; TPPack reduces total wire-length and minimal channel width by 20.0% and 20.2% with a 9.0% performance gain. These results are achieved at no loss of utilization.

K-way partitioning based packing for FPGA logic blocks without input bandwidth constraint

Low-cost FPGAs have comparable number of Configurable Logic Blocks (CLBs) with respect to resource-rich FPGAs but have much less routing tracks. For CAD tools, this situation increases the difficulty of successfully mapping a circuit into the low-cost FPGAs. Instead of switching to resource-rich FPGAs, the designers could employ depopulation-based clustering techniques which underuse CLBs, hence improve routability by spreading the logic over the architecture. However, all depopulation-based clustering algorithms to this date increase critical path delay. In this paper, we present a timing-driven nonuniform depopulation-based clustering technique, T-NDPack, that targets critical path delay and channel width constraints simultaneously. T-NDPack adjusts the CLB capacity based on the criticality of the Basic Logic Element (BLE). Results show that T-NDPack reduces minimum channel width by 11.07% while increasing the number of CLBs by 13.28% compared to T-VPack. More importantly, T-NDPack decreases critical path delay by 2.89%.

/pdf/timing-driven-nonuniform-depopulation-based-clustering-1sl9xvjr5y.pdf

Timing-driven nonuniform depopulation-based clustering

Low-cost FPGAs have comparable number of Configurable Logic Blocks (CLBs) with respect to resource-rich FPGAs but have much less routing tracks. This leads to the difficulty for CAD tools to successfully and optimally map a circuit into these devices. Instead of switching to resource-rich FPGAs, the designers could employ depopulation based clustering technique which underuses CLBs, hence improves routability by spreading the logic over the architecture. However, all depopulation based clustering algorithms to this date increase critical path delay. In this paper, we present a timing-driven non-uniform depopulation based clustering technique, T-NDPack, that targets critical path delay and channel width constraints simultaneously. We adjust the capacity of the CLB based on the criticality of the logic block. Paper analyzes the effect of depopulation strategies on area and delay performance. Results show that T-NDPack reduces minimum channel width by 11.07% while increasing the number of CLBs by 13.28%. More importantly, T-NDPack decreases critical path delay by 2.89%.

T-NDPack: Timing-driven non-uniform depopulation based clustering

In FPGA CAD flow, the clustering stage builds the foundation for placement and routing stages and affects performance parameters, such as routability, delay, and channel width significantly. Net sharing and criticality are the two most commonly used factors in clustering cost functions. With this study, we first derive a third term, net-length factor, and then design a generic method for integrating net length into the clustering algorithms. Net-length factor enables characterizing the nets based on the routing stress they might cause during later stages of the CAD flow and is essential for enhancing the routability of the design. We evaluate the effectiveness of integrating net length as a factor into the well-known timing (T-VPack)-, depopulation (T-NDPack)-, and routability (iRAC and T-RPack)-driven clustering algorithms. Through exhaustive experimental studies, we show that net-length factor consistently helps improve the channel-width performance of routability-, depopulation-, and timing-driven clustering algorithms that do not explicitly target low fan-out nets in their cost functions. Particularly, net-length factor leads to average reduction in channel width for T-VPack, T-RPack, and T-NDPack by 11.6p, 10.8p, and 14.2p, respectively, and in a majority of the cases, improves the critical-path delay without increasing the array size.

Hanyu Liu

Papers

Timing-driven nonuniform depopulation-based clustering

T-NDPack: Timing-driven non-uniform depopulation based clustering

Integration of Net-Length Factor with Timing- and Routability-Driven Clustering Algorithms