This paper will discuss the design and construction of BESIII, which is designed to study physics in the τ -charm energy region utilizing the new high luminosity BEPCII double ring e + e − collider. The expected performance will be given based on Monte Carlo simulations and results of cosmic ray and beam tests. In BESIII, tracking and momentum measurements for charged particles are made by a cylindrical multilayer drift chamber in a 1 T superconducting solenoid. Charged particles are identified with a time-of-flight system based on plastic scintillators in conjunction with dE/dx (energy loss per unit pathlength) measurements in the drift chamber. Energies of electromagnetic showers are measured by a CsI(Tl) crystal calorimeter located inside the solenoid magnet. Muons are identified by arrays of resistive plate chambers in a steel magnetic yoke for the flux return. The level 1 trigger system, data acquisition system and the detector control system based on networked computers will also be described.

Design and construction of the BESIII detector

HADES is a running spectrometer installed at GSI, Germany. PANDA and CBM are planned detector systems for the new FAIR facility at GSI. For these detectors, a general-purpose trigger and readout board with on-board DAQ functionality was developed. The original motivation for this project was the implementation of a 128-channel time to digital converter (TDC) with a time resolution of sigma=40 ps based on the HPTDC chip from CERN into a fully fledged data acquisition system. The application of the board is detector independent, includes a 2 Gbit/s optical link and has the option to employ the TDC chips and/or to integrate versatile add-on boards through 16 Gbit/s connectors. The latter one may interface to the front end electronics of other types of detectors. A large FPGA (Xilinx Virtex 4 LX40) and a TigerSharc DSP can be used as on-board resources for trigger and on-line analysis algorithms. Data transfer to mass storage and slow control is done via an ETRAX processor running Linux and a 100 Mbit/s Ethernet interface.

A General Purpose Trigger and Readout Board for HADES and FAIR-Experiments

HADES is a running spectrometer installed at GSI,Germany. PANDA and CBM are planned detector systems for the new FAIR facility at GSI. For these detectors, a general-purpose trigger and readout board (TRB) with on-board DAQ functionality was developed. Data readout and slow control is done via an Etrax processor running Linux and a 100 Mbit/s Ethernet interface. The original motivation and application of the hardware is the implementation of a 128-channel Time to Digital Converter (TDC) electronics based on the HPTDC from CERN (we achieve sigma = 40 ps resolution). However, it has been developed in a way to be detector independent and thus may serve for any high-speed data acquisition by using a flexible add-on board concept (interface connector 15 Gbit/s) and an optical link (2 Gbit/s). A large FPGA (Xilinx Virtex 4 LX40) and a TigerSharc DSP can be used as on-board resources for trigger and on-line analysis algorithms.

....................................................................................................ii ACKNOWLEDGEMENTS ................................................................................. iv TABLE OF CONTENTS ....................................................................................... v LIST OF TABLES .............................................................................................. viii LIST OF FIGURES .............................................................................................. ix LIST OF ABBREVIATIONS ..............................................................................xii CHAPTER 1 GENERAL INTRODUCTION ..................................................... 1 1.1 Traditional Medicine and Folk Medicinal Herbs ....................................... 2 1.2 Background Information of Isodon and Xihuangcao ................................ 4 1.3 Previous Studies on Xihuangcao ............................................................... 6 1.3.1 Origin Plants and Resources Survey of Xihuangcao ...................... 6 1.3.2 Authentication of Source Plants ...................................................... 7 1.3.3 Chemical Constituents .................................................................... 8 1.3.4 Pharmacological Studies ............................................................... 18 1.3.5 Quality Control ............................................................................. 20 1.3.6 Other Studies ................................................................................. 21 1.4 Objectives and Design of This Study....................................................... 22 CHAPTER 2 TEXTUAL RESEARCH AND FIELD INVESTIGATION ON THE BOTANICAL ORIGINS ................................................ 23 2.1 Taxonomy of the Original Plants ............................................................. 24 2.2 Botanical Origins of Xihuangcao Documented in Literatures ................. 29 2.2.1 In Herbal Documents .................................................................... 29

Pharmacognostic studies on folk medicinal herb xihuangcao

We present an FPGA-based online data reduction system for the pixel detector of the future Belle II experiment. The occupancy of the pixel detector is estimated at 3 %. This corresponds to a data output rate of more than 20 GB/s after zero suppression, dominated by background. The Online Selection Nodes (ONSEN) system aims to reduce the background data by a factor of 30. It consists of 33 MicroTCA cards, each equipped with a Xilinx Virtex-5 FPGA and 4 GiB DDR2 RAM. These cards are hosted by 9 AdvancedTCA carrier boards. The ONSEN system buffers the entire output data from the pixel detector for up to 5 seconds. During this time, the Belle II high-level trigger PC farm performs an online event reconstruction, using data from the other Belle II subdetectors. It extrapolates reconstructed tracks to the layers of the pixel detector and defines regions of interest around the intercepts. Based on this information, the ONSEN system discards all pixels not inside a region of interest before sending the remaining hits to the event builder system. During a beam test with one layer of the pixel detector and four layers of the surrounding silicon strip detector, including a scaled-down version of the high-level trigger and data acquisition system, the pixel data reduction using regions of interest was exercised. We investigated the data produced in more than 20 million events and verified that the ONSEN system behaved correctly, forwarding all pixels inside regions of interest and discarding the rest.

The ONSEN Data Reduction System for the Belle II Pixel Detector

PANDA is a new universal detector for antiproton physics at the HESR facility at FAIR/GSI. The PANDA data acquisition system has to handle interaction rates of the order of 10**7 /s and data rates of several 100 Gb Is. FPGA based compute nodes with multi-Gbit/s bandwidth capability using the ATCA architecture are designed to handle tasks such as event building, feature extraction and high level trigger processing. Each board is equipped with 5 Virtex4 FX60 FPGAs. High bandwidth connectivity is provided by four Gbit Ethernet links and 8 additional optical links connected to RocketIO ports. A single ATCA crate can host up to 14 boards which are interconnected via a full mesh backplane.

/pdf/fpga-based-compute-nodes-for-the-panda-experiment-at-fair-4r1ajlbmze.pdf

FPGA - Based Compute Nodes for the PANDA Experiment at FAIR

The upcoming Belle II experiment is designed to work at a luminosity of 8×1035 cm-2s-1, 40 times higher than its predecessor. The pixel detector of Belle II with its ~ 8 million channels will deliver ten times more data than all other sub-detectors together. A data rate of 22 Gbytes/s is expected for a trigger rate of 30 kHz and an estimated pixel detector occupancy of 3%, which is by far exceeding the specifications of the Belle II event builder system. Therefore a realtime data reduction of a factor > 30 is needed. A hardware platform capable of processing this amount of data is the ATCA based Compute Node (CN). Each CN consists of an xTCA carrier board and four AMC/xTCA daughter boards. The carrier board supplies the high bandwidth connectivity to the other CNs via Rocket-IO links. In the current prototype design, each AMC board is equipped with a Xilinx Virtex-5 FX70T FPGA, 4 GB of memory, Gbit Ethernet and two bi-directional optical links allowing for a bandwidth of up to 12.5 Gbits/s. IPMI control of mother and daughter board is foreseen. One ATCA shelf containing 10 mother boards/40 daughter boards is sufficient to process the data from the 40 front end boards. The data reduction on the CN is done in two steps. First, the event data delivered by the front end electronics via optical links is stored in memory until the high level trigger (HLT) decision has been made. The HLT rejects >2/3 of these events. In a second step, pixel data of positively triggered events is reduced with the help of regions of interest (ROI), calculated by the HLT from projecting trajectories back to the pixel detector plane. The design allows additional ROI inputs computed from hit cluster properties or tracklets from the surrounding silicon strip detector. The final data reduction is achieved by sending only data within these ROIs to the main event builder.

The Belle II pixel detector data acquisition and reduction system

An ATCA-based computation platform for data acquisition and trigger applications in nuclear and particle physics experiments has been developed. Each compute node (CN) which appears as a field replaceable unit (FRU) in an ATCA shelf, features 5 Xilinx Virtex-4 FX60 FPGAs and up to 10 GBytes DDR2 memory. Connectivity is provided with 8 optical links and 5 Gigabit Ethernet ports, which are mounted on each board to receive data from detectors and forward results to outer shelves or PC farms with attached mass storage. Fast point-to-point on-board interconnections between FPGAs as well as the full-mesh shelf backplane provide flexibility and high bandwidth to partition algorithms and correlate results among them. The system represents a highly reconfigurable and scalable solution for multiple applications.

/pdf/atca-based-computation-platform-for-data-acquisition-and-265ssoig9x.pdf

ATCA-based computation platform for data acquisition and triggering in particle physics experiments

An ATCA-based computation platform for data acquisition and trigger(TDAQ) applications has been developed for multiple future projects such as PANDA, HADES, and BESIII. Each Compute Node (CN) appears as one of the fourteen Field Replaceable Units (FRU) in an ATCA shelf, which in total features a high performance of 1890 Gbps inter-FPGA onboard channels, 1456 Gbps inter-board backplane connections, 728 Gbps full-duplex optical links, 70 Gbps Ethernet, 140 GBytes DDR2 SDRAM, and all computing resources of 70 Xilinx Virtex-4 FX60 FPGAs. Corresponding to the system architecture, a hardware/software co-design approach is proposed to ease and accelerate the development for different experiments. In the uniform system design, application-specific computation is to be implemented as customized hardware co-processors, while the embedded PowerPC processor takes charge of flexible slow controls and transmission protocol processing.

Hardware/software co-design of an ATCA-based computation platform for data acquisition and triggering

The trigger system of Beijing Spectrometer III, part of the upgrade of Beijing Electron Positron Collider, has been designed and implemented, and is ready for installation. This paper describes briefly the system components, its characteristics, and some technical issues. The system consists mainly of four parts: MDC (drift chamber) tracking subsystem, EMC (electromagnetic calorimeter) subsystem, TOF (time of flight) subsystem and global trigger. Some highlights in designing of this system includes: trigger scheme optimization with software simulation; optical transmission between trigger and FEEs to realize isolation with FEEs to avoid ground loop current interference; designed with most latest FPGA (Xilinx Spartan 3, VirtexII Pro...) for simplicity, high reliability and easy maintenance and hence smaller system; FPGA in-system programming or firmware online downloadable via onboard, panel connector and/or VME bus for modification flexibility during commissioning. Different from the usual fix delay data transmission from FEE to trigger, the RocketIO has been used as SEDES.

Hao Xu

Papers

FPGA - Based Compute Nodes for the PANDA Experiment at FAIR

The Belle II pixel detector data acquisition and reduction system

ATCA-based computation platform for data acquisition and triggering in particle physics experiments

Hardware/software co-design of an ATCA-based computation platform for data acquisition and triggering

Trigger System of BESIII