We present an analog-integrated circuit implementation of long short-term memory network, which is compatible with digital CMOS technology. We have used multiple-input floating gate MOSFETs as both the front-end to obtain converted analog signals and the differential pairs in proposed analog multipliers. Analog crossbar is built by the analog multiplier processing matrix and bitwise multiplications. We have shown that using current signals as internal transmission signals can largely reduce computation delay, compared to the digital implementation. We also have introduced analog blocks to work as activation functions for the algorithm. In the back-end of our design, we have used current comparators to achieve the output to be readable to external digital systems. We have designed the LSTM network with the matrix size of 16 × 16 in TSMC 180nm CMOS technology. The post-layout simulations show that the latency of one computing cycle is 1.19ns without memory, and power dissipation of the single analog LSTM computing core with 2 kilobytes SRAM at 200MHz is 460.3mW. The overhead of power dissipation due to SRAM access is 8.3%, in which the computing of each LSTM layer requires one computing cycle. The energy efficiency is 0.95TOP/s/W.

https://dl.acm.org/doi/pdf/10.1145/3289393

Long Short-Term Memory Network Design for Analog Computing

The viability of bus interconnection models is explored, using the multiple-valued logic (MVL) paradigm to reduce the cost and energy consumption of off-chip and on-chip address, data and instruction buses within system-on-a-chip platforms. Data can be transferred over the buses using ternary, balanced ternary or quaternary number systems, rather than binary. This allows more compact bus design with a fewer number of bus lines, which can result in lower input/output pin cost for off-chip buses. Reducing the number of bus lines also allows us to increase the distance between the adjacent bus lines using the same silicon area. This further reduces interwire capacitance and may lead to significant on-chip bus energy reduction for low-power embedded systems. First, a combinatorial probabilistic view of digit transition patterns in binary and MVL number systems is provided. This is followed by an empirical study conducted by running various applications to measure bus switching activities as well as total bus energy consumption of real-world applications. It is observed that the number of bus transitions in a multiple-valued bus, particularly in a quaternary bus, is significantly less than the number of bus transitions in a binary bus. Our experimental results show that MVL bus models, replacing the binary equivalent, can be viable interconnection structures and are able to provide up to 29, 29 and 30% reduction in energy consumption for off-chip address, data and instruction buses, respectively. These savings are 55, 53 and 62% for on-chip quaternary address, data and instruction buses, respectively using 0.25 /spl mu/m technology.

Multiple-valued logic buses for reducing bus energy in low-power systems

Quaternary to binary bit conversion CMOS integrated circuit design using multiple-input floating gate MOSFETS

ii Acknowledgments I would like to take this opportunity to thank everyone who contributed to the successful completion of this thesis. First of all, I would like to thank Dr. Ashok Srivastava, my major professor, for providing extensive support and encouragement throughout this work. I would also like to thank Dr. Kak for being a part of my committee. Center for Computation & Technology for supporting me financially during my stay at LSU. I would like to thank my parents Prabhavathi and Murali Krishna and to all my family members and friends for their constant prayers and moral support throughout my life. I deeply thank my mother for her efforts to make me successful. Special thanks to my brother, sisters and brother-in-laws for all their love and support. I also thank Anand for his help in my work and all my other friends, Satish, at times I needed them. I also thank all my friends at LSU who helped me indirectly in my work. Last of all I thank GOD for keeping me in good health and spirits throughout my stay at LSU.

/pdf/first-order-sigma-delta-modulator-of-an-oversampling-adc-3aqvrj71fo.pdf

First order sigma-delta modulator of an oversampling ADC design in CMOS using floating gate MOSFETS

In this paper, we propose three novel cache models using multiple-valued logic (MVL) paradigm to reduce the cache data storage area and cache energy consumption for embedded systems. Multiple-valued caches have significant potential for compact and power-efficient cache array design. The cache models differ from each other depending on whether they store tag and data in binary, radix-r or a mix of both. Our analytical study of cache silicon area shows that an embedded system-on-a-chip (SoC) equipped with a multiple-valued cache model can reduce the cache data storage area up to 6% regardless of cache parameters. Also, our experiments on several embedded benchmarks demonstrate that dynamic cache energy consumption can be reduced up to 62% in a multiple-valued instruction cache in an embedded SoC.

/pdf/multiple-valued-caches-for-power-efficient-embedded-systems-1cbb0e5aq7.pdf

Multiple-valued caches for power-efficient embedded systems

ii Acknowledgements I would like to dedicate my work to my parents, Mr. and Mrs. G. Garataiah and my sister Prashanthi, for their constant prayers and encouragement throughout my life. I am very grateful to my advisor Dr. A. Srivastava for his guidance, patience and understanding throughout this work. His suggestions, discussions and constant encouragement have helped me to get a deep insight in the field of VLSI design. I would like to thank Dr. P. K. Ajmera for his valuable guidance in the courses I took with him and for being a part of my committee. I would also like to thank Dr. Martin Feldman for being a part of my committee. Arun, Kamesh, Lakky and Anand for their help and encouragement at times I needed them. I would also like to thank all my friends here who made my stay at LSU an enjoyable and a memorable one. Last of all I thank GOD for keeping me in good health and spirits throughout my stay at LSU. 4.8 Output at MSB is compared with simulation data with MOS model parameters used before and after fabrication and fabricated chip ..

/pdf/ternary-and-quaternary-logic-to-binary-bit-conversion-cmos-1izmluqqgz.pdf

Harish N Venkata

Papers

Ternary and quaternary logic to binary bit conversion CMOS integrated circuit design using multiple input floating gate MOSFETs