Switching currents of simultaneous switching output (SSO) buffers can cause significant power-supply-induced jitter (PSIJ) and uncertainty in the output voltages The bit error rate (BER) can be simulated by considering all possible input data patterns with a long data sequence; however, it requires large computational efforts In this paper, the SSO waveforms are analytically calculated, including the rise time of the input voltage, and the probability density functions (PDFs) of the waveforms are analytically calculated The PDFs of the SSO step responses are combined with the inter-symbol interference (ISI) PDF extraction The statistical eye and BER eye diagrams obtained from the proposed method are validated with HSPICE simulations The effects of the SSO patterns as well as the channel ISI are successfully included in the proposed method Also, the effects of input rise time and the number of parallel SSO buffers are investigated, and the proposed method is extended for analysis of SSO buffers with the data bus inversion (DBI) coding The method should be practically useful for design of wideband memory I/O interfaces and low-cost consumer devices by reducing the computational time of the jitter and BER drastically

Statistical Analysis for Pattern-Dependent Simultaneous Switching Outputs (SSO) of Parallel Single-Ended Buffers

Ultrathin 3-D glass interposers with through-package vias at the same pitch as through-silicon vias (TSVs) have been proposed as a simpler and cheaper alternative to the direct 3-D stacking of logic and memory devices. Such 3-D interposers provide wide-I/O channels for high signal bandwidth (BW) between the logic device on one side of the interposer and memory stack on the other side, without the use of complex TSVs in the logic die. However, this configuration introduces power delivery design challenges due to resonance from: 1) the low-loss property of the glass substrate and 2) the parasitic inductance due to additional length from lateral power delivery path. This paper presents for the first time, the design and demonstration of power delivery networks (PDNs) in 30- $\mu \text{m}$ thin, 3-D double-sided glass interposers, by suppressing the noise from mode resonances. The self-impedance of the 3-D glass interposer PDN was simulated using electromagnetic solvers, including printed-wiring-board and chip-level models. The 3-D PDN was compared with that of the 2-D glass packages having fully populated ball grid array connections. The resonance mechanism for each configuration was studied in detail, and the corresponding PDN loop inductances were evaluated. High impedance peaks in addition to the 2-D PDN were observed at high frequencies (near 7.3 GHz) in the 3-D interposer structure due to the increased inductances from lateral power delivery. This paper proposes and evaluates three important resonance suppression techniques based on: 1) 3-D interposer die configuration; 2) the selection and placement of decoupling capacitors; and 3) 3-D interposer package power and ground stack-up. Two-metal and four-metal layer test vehicles were fabricated on 30- and 100- $\mu \text{m}$ thick panel-based glass substrates, respectively, to validate the modeling and analysis of the proposed approach. The PDN test structures were characterized up to 20 GHz for plane resonances and network impedances, with good model-to-hardware correlation. The results in this paper suggest that the ultrathin 3-D interposer PDN structure can be effectively designed to meet the target impedance guidelines for high-BW applications, providing a compelling alternative to 3-D-IC stacking with the TSVs.

Design and Demonstration of Power Delivery Networks With Effective Resonance Suppression in Double-Sided 3-D Glass Interposer Packages

On-Chip Waveform Capture and Diagnosis of Power Delivery in SoC Integration

The output voltages at parallel simultaneous switching output (SSO) channels are affected by impedance of power distribution network (PDN) and SSO patterns. In this paper, a target impedance for PDN is directly extracted from the allowable signal output variations due to the SSO patterns.

Novel target impedance for power distribution network of simultaneous switching output (SSO) buffers

In this paper, analytical models of on-chip power noise induced by an on-chip linear voltage regulator module (VRM) circuit with a high-speed output buffer are proposed. Based on the piecewise linear approximated mosfet I – V curve model, closed-form equations for the on-chip power noise induced by an on-chip low-dropout regulator are derived. The accuracy of the proposed analytical model is validated by SPICE simulation with a 110-nm CMOS technology library. Based on the proposed analytical models, the impacts of VRM design parameters on VRM output noise induced by load current and external noises are analyzed. Because self-impedance at the VRM output and external noise transfer functions share a common resonant frequency, the on-chip power noise is minimized by avoiding the resonant frequency from peak frequencies of noise source spectrums. The larger on-chip decoupling capacitance at load reduces, the overall on-chip VRM output noise. While the larger pass transistor size reduces the on-chip VRM output noise induced by the reference voltage fluctuation, it increases the noise generated by off-chip power fluctuation. The reference voltage node needs to be carefully designed, as opposed to an off-chip power distribution network, due to its dominant impact on the on-chip VRM output noise. The analysis results based on the proposed model provide an in-depth understanding of and useful design guidance for on-chip power noise induced by the on-chip linear VRM with a high-speed output buffer.

Modeling and Analysis of On-Chip Power Noise Induced by an On-Chip Linear Voltage Regulator Module With a High-Speed Output Buffer

Because CMOS LSIs operate at higher clock frequencies in recent years, conventional methods for obeying EMC regulations are not sufficient only at package level and board level So chip level counter-measure is even more important to reduce EMI as an excitation source of noise In this paper, power supply noise was evaluated by fabricating two circuit blocks in a test chip One was with on-chip capacitance consisted of intentional MOS (metal-oxide semiconductor) capacitors and MIM (metal-insulator-metal) capacitors, and the other was without any intentional capacitors Reduction effect of power supply noise and the impedance of PDN (power distribution network) at each circuit block were evaluated based on chip-package-board co-design It has been found that PDN Impedance was suppressed by implementing on-chip capacitance in the high frequency region

Evaluation of PDN impedance and power supply noise for different on-chip decoupling structures

The this paper deals with the analysis of power distribution network (PDN) impedance and simultaneous switching output buffer (SSO) noise for a 3D system-in package (SiP) with 4k-IO widebus structure The 3D SiP consisted of 3 stacked chips (a memory chip on the top, Si interposer in the middle, and a logic chip) and an organic package substrate More than 4096 of through silicon vias (TSV's) were formed to the silicon interposer and the logic chip The PDN impedance for each chip was extracted by using XcitePI (Sigrity Inc) Then, the PDN impedance for the organic package substrate was extracted by using SIwave (Ansys Inc) Finally, the total PDN impedance was synthesized to estimate the power supply disturbance due to the anti-resonance peak

Analysis and characterization of PDN impedance and SSO noise of 4k-IO 3D SiP

Simultaneous switching output buffer (SSO) noise and impedance of power distribution network (PDN) for a 3D systemin package (SiP) with 4k-IO widebus structure has been investigated. The 3D SiP consisted of 3 stacked chips and an organic interposer. These three chips were a memory chip on the top, a silicon interposer in the middle, and a logic chip on the bottom. The size of each chip was the same, and 9.93 mm by 9.93 mm. More than 4096 of through silicon vias (TSV's) were formed to the silicon interposer. Next, these 3 stacked chips were assembled on the organic interposer, whose size was 26 mm by 26mm. SSO noise is one of critical issues for the 3D SiP with 4k-IO widebus structure. So, the SSO noise was measured in the miniIO power supply system in an evaluation board. Furthermore the PDN impedance for each chip was measured by direct contact method. Then, the total PDN impedance was synthesized to confirm the anti-resonance peak of it.

Measurement of SSO noise and PDN impedance of 3D SiP with 4k-IO widebus structure

Parasitic inductance that exists in a package induces SSN (Simultaneous Switching Noise) and timing jitter. These noises cause malfunction of LSI and systems. The goal of this paper is to clarify the influence of the effective inductance of the package including mutual inductance by changing the number of simultaneously switching buffers and alternating adjacent buffers in the reverse direction each other. In this study, measured SSNs were reproduced by HSPICE simulation. The whole simulation model consisted of on-chip PDN (Power Distribution Network), package PDN and board PDN, along with I/O buffer model. The simulated SSN waveforms agreed well with the measured results.

Measurement and analysis of SSN and Jitter of FPGA

The 4096 bits wide-bus three-dimensional integration device using through-silicon-vias (TSVs) has been designed and fabricated as a demonstrator for power integrity such as power distribution network (PDN) impedance and simultaneous switching output (SSO) noise characteristics. Anti-resonance peak of total PDN impedance was extracted at around 80 MHz. This result was well coincident with maximum SSO noise frequency at around 75 MHz. Further, SSO noise reduction clocking named phase-shift clock has also been implemented to demonstrate the effectiveness as measurement basis.

Haruya Fujita

Papers

Evaluation of PDN impedance and power supply noise for different on-chip decoupling structures

Analysis and characterization of PDN impedance and SSO noise of 4k-IO 3D SiP

Measurement of SSO noise and PDN impedance of 3D SiP with 4k-IO widebus structure

Measurement and analysis of SSN and Jitter of FPGA

PDN characteristics of 3D-SiP with a wide-bus structure under 4k-IO operations