Switching currents of simultaneous switching output (SSO) buffers can cause significant power-supply-induced jitter (PSIJ) and uncertainty in the output voltages The bit error rate (BER) can be simulated by considering all possible input data patterns with a long data sequence; however, it requires large computational efforts In this paper, the SSO waveforms are analytically calculated, including the rise time of the input voltage, and the probability density functions (PDFs) of the waveforms are analytically calculated The PDFs of the SSO step responses are combined with the inter-symbol interference (ISI) PDF extraction The statistical eye and BER eye diagrams obtained from the proposed method are validated with HSPICE simulations The effects of the SSO patterns as well as the channel ISI are successfully included in the proposed method Also, the effects of input rise time and the number of parallel SSO buffers are investigated, and the proposed method is extended for analysis of SSO buffers with the data bus inversion (DBI) coding The method should be practically useful for design of wideband memory I/O interfaces and low-cost consumer devices by reducing the computational time of the jitter and BER drastically

Statistical Analysis for Pattern-Dependent Simultaneous Switching Outputs (SSO) of Parallel Single-Ended Buffers

Ultrathin 3-D glass interposers with through-package vias at the same pitch as through-silicon vias (TSVs) have been proposed as a simpler and cheaper alternative to the direct 3-D stacking of logic and memory devices. Such 3-D interposers provide wide-I/O channels for high signal bandwidth (BW) between the logic device on one side of the interposer and memory stack on the other side, without the use of complex TSVs in the logic die. However, this configuration introduces power delivery design challenges due to resonance from: 1) the low-loss property of the glass substrate and 2) the parasitic inductance due to additional length from lateral power delivery path. This paper presents for the first time, the design and demonstration of power delivery networks (PDNs) in 30- $\mu \text{m}$ thin, 3-D double-sided glass interposers, by suppressing the noise from mode resonances. The self-impedance of the 3-D glass interposer PDN was simulated using electromagnetic solvers, including printed-wiring-board and chip-level models. The 3-D PDN was compared with that of the 2-D glass packages having fully populated ball grid array connections. The resonance mechanism for each configuration was studied in detail, and the corresponding PDN loop inductances were evaluated. High impedance peaks in addition to the 2-D PDN were observed at high frequencies (near 7.3 GHz) in the 3-D interposer structure due to the increased inductances from lateral power delivery. This paper proposes and evaluates three important resonance suppression techniques based on: 1) 3-D interposer die configuration; 2) the selection and placement of decoupling capacitors; and 3) 3-D interposer package power and ground stack-up. Two-metal and four-metal layer test vehicles were fabricated on 30- and 100- $\mu \text{m}$ thick panel-based glass substrates, respectively, to validate the modeling and analysis of the proposed approach. The PDN test structures were characterized up to 20 GHz for plane resonances and network impedances, with good model-to-hardware correlation. The results in this paper suggest that the ultrathin 3-D interposer PDN structure can be effectively designed to meet the target impedance guidelines for high-BW applications, providing a compelling alternative to 3-D-IC stacking with the TSVs.

Design and Demonstration of Power Delivery Networks With Effective Resonance Suppression in Double-Sided 3-D Glass Interposer Packages

The output voltages at parallel simultaneous switching output (SSO) channels are affected by impedance of power distribution network (PDN) and SSO patterns. In this paper, a target impedance for PDN is directly extracted from the allowable signal output variations due to the SSO patterns.

Novel target impedance for power distribution network of simultaneous switching output (SSO) buffers

The present methodology of clock distribution inside high-performance central processing unit chip offers current to ramp linearly or exponentially when the chip comes out of sleep mode to active mode or when the clock starts driving a chip to operate. This linear current ramp leads to power and ground noise due to Ldi/dt. In this paper, we have shown that for a given power delivery network (PDN), it is possible to generate a current profile (current versus time), by controlling the current on all the complementary metal oxide semiconductor gates of the clock generation circuits. In our methodology, the time for the chip to reach the maximum saturation current is same when compared with the present linear current ramp methodology. We have also developed a new “optimizer program” to show the existence of a unique single current profile solution, which is different from the present methodology. The proposed method requires understanding of how the minimum value of the power supply voltage (supposed to be always 1V for the device) gets changed, when various gates in a clock tree are turned ON at different times (Tn, parameters of the problem) with different values of current (In, other parameters of the problem). Basically, an ensemble of “n” number of transistors will be turned ON at time t=Tn while it will pump the total current I=In. This understanding generates the derivative function of the minimum noise point with respect to these said parameters, which in turn generates a new set of parameters to optimize the noise point. We have found that this optimizer program works and also converges for the generation of minimum power and ground noise, which is 40% lesser than the conventional approach.

A New Current Profile Determination Methodology Incorporating Gating Logic to Minimize the Noise of CPU Chip by 40

An equivalent circuit model for simultaneous switching output (SSO) drivers is constructed. The simultaneous differential equations for the pattern-dependent SSO waveforms are built from the model and analytically solved. The analytical solutions are validated by comparison with the HSPICE simulation results. The effects of the number of pull-up and pull-down transitions are also investigated from the case studies.

Analytical calculation of pattern-dependent simultaneous switching outputs (SSO) due to power supply fluctuations

The this paper deals with the analysis of power distribution network (PDN) impedance and simultaneous switching output buffer (SSO) noise for a 3D system-in package (SiP) with 4k-IO widebus structure The 3D SiP consisted of 3 stacked chips (a memory chip on the top, Si interposer in the middle, and a logic chip) and an organic package substrate More than 4096 of through silicon vias (TSV's) were formed to the silicon interposer and the logic chip The PDN impedance for each chip was extracted by using XcitePI (Sigrity Inc) Then, the PDN impedance for the organic package substrate was extracted by using SIwave (Ansys Inc) Finally, the total PDN impedance was synthesized to estimate the power supply disturbance due to the anti-resonance peak

Analysis and characterization of PDN impedance and SSO noise of 4k-IO 3D SiP

The 4096 bits wide-bus three-dimensional integration device using through-silicon-vias (TSVs) has been designed and fabricated as a demonstrator for power integrity such as power distribution network (PDN) impedance and simultaneous switching output (SSO) noise characteristics. Anti-resonance peak of total PDN impedance was extracted at around 80 MHz. This result was well coincident with maximum SSO noise frequency at around 75 MHz. Further, SSO noise reduction clocking named phase-shift clock has also been implemented to demonstrate the effectiveness as measurement basis.

S. Uchiyama

Papers

Analysis and characterization of PDN impedance and SSO noise of 4k-IO 3D SiP

PDN characteristics of 3D-SiP with a wide-bus structure under 4k-IO operations