A display panel is formed using essentially single crystal thin-film material that is transferred to substrates for display fabrication. Pixel arrays form light valves or switches that can be fabricated with control electronics in the thin-film material prior to transfer. The resulting circuit panel is than incorporated into a display panel with a light emitting or liquid crystal material to provide the desired display.

Single crystal silicon arrayed devices for display panels

The invention relates to device processing, packaging and interconnects that will yield integrated electronic circuitry of higher density and complexity than can be obtained by using conventional multi-chip modules. Processes include the formation of complex multi-function circuitry on common module substrates using circuit tiles of silicon thin-films which are transferred, interconnected and packaged. Circuit modules using integrated transfer/interconnect processes compatible with extremely high density and complexity provide large-area active-matrix displays with on-board drivers and logic in a complete glass-based modules. Other applications are contemplated, such as, displays, microprocessor and memory devices, and communication circuits with optical input and output.

High density electronic circuit modules

A method of providing a first and a second Silicon-on-Insulator (SOI) wafer, wherein each SOI wafer includes a silicon layer separated from a bulk silicon substrate by a layer of dielectric material, typically SiO2. Next, at least one electrical feedthrough is formed in each of the silicon layers and active and passive devices are formed in each of the thin silicon layers. Next, interconnects are formed that overlie the silicon layer and are electrically coupled to the feedthrough. One of the wafers is then attached to a temporary substrate such that the interconnects are interposed between the thin silicon layer and the temporary substrate. The bulk silicon substrate of the wafer having the temporary substrate is then etched to expose the dielectric layer. Further interconnects are then formed through the exposed dielectric layer for electrically contacting the at least one feedthrough. This results in the formation of a first circuit assembly. A next step then couples the further interconnects of the circuit assembly to the interconnects of the second SOI wafer, the second SOI wafer having a bulk substrate, a dielectric layer overlying a surface of the substrate, and a layer of processed silicon overlying the dielectric layer. The temporary substrate is then removed. Additional circuit assemblies may then be stacked and interconnected to form a 3d integrated circuit.

Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substrate

A method and structure for fabricating an electronic device using an SOI technique that results in formation of a buried oxide layer. The method includes fabricating at least one first component of the electronic device and fabricating at least one second component of the electronic device, wherein the first component and the second component are on opposite sides of the buried oxide layer, thereby causing the buried oxide layer to perform a function within the electronic device. Entire circuits can be designed around this technique.

Method and structure for buried circuits and devices

The invention relates to device processing, packaging and interconnects that will yield integrated electronic circuitry of high density and complexity. Processes include the formation of complex multi-function circuitry on common module substrates using circuit tiles of silicon thin-films which are transferred, interconnected and packaged. Circuit modules using integrated transfer/interconnect processes compatible with extremely high density and complexity provide large-area active-matrix displays with on-board drivers and logic in modules.

Method for manufacturing a semiconductor device using a circuit transfer film

The present invention relates to a semiconductor device in which a semiconductor element is formed on a semiconductor layer (3) supported on a substrate (1) via at least insulating layers (2) and (4) as shown in FIGS. 1 and 2 and a method of fabricating the same. The semiconductor layer (3) has wiring layers (5) and (6) on both surfaces thereof, thus leading itself well for increasing the density of wiring and for increasing the operation speed in a large-scale integrated circuit device.

Method of making a thin film transistor

A semiconductor device comprising a silicon substrate with an oxygen doped polycrystalline or amorphous silicon layer formed on the substrate so as to form a hetero junction therewith. A transistor formed according to the invention has an emitter-base hetero junction and has a high current gain.

Semiconductor device having a hetero junction

A semiconductor device is provided having at least two semiconductor regions of opposite conductivity type and forming a planar-type PN junction. A field limiting ring is disposed spaced from the PN junction. A high-resistivity polycrystalline silicon layer covers the PN junction and the field limiting ring.

Semiconductor device with a high breakdown voltage characteristic

A method of an iron Fe ion implantation into a semiconductor substrate of an N-type conductivity is disclosed. The method comprises the steps of implanting Fe ions into an N-type semiconductor substrate from its one surface with the dose amount of 10 10 to 10 15 cm -2 and heat-treating the semiconductor substrate with Fe ions at 850° to 1250° C. to control the lifetime of the minority carrier in the substrate and hence to reduce the temperature dependency of the lifetime.

Hayashi Hisao

Papers

Method of making a thin film transistor

Semiconductor device having a hetero junction

Semiconductor device with a high breakdown voltage characteristic

Fe Ion implantation into semiconductor substrate for reduced lifetime sensitivity to temperature

Halbleiterbauelement mit heterouebergang