The advent of multicore processors has renewed interest in the idea of incorporating transactions into the programming model used to write parallel programs. This approach, known as transactional memory, offers an alternative, and hopefully better, way to coordinate concurrent threads. The ACI (atomicity, consistency, isolation) properties of transactions provide a foundation to ensure that concurrent reads and writes of shared data do not produce inconsistent or incorrect results. At a higher level, a computation wrapped in a transaction executes atomically - either it completes successfully and commits its result in its entirety or it aborts. In addition, isolation ensures the transaction produces the same result as if no other transactions were executing concurrently. Although transactions are not a parallel programming panacea, they shift much of the burden of synchronizing and coordinating parallel computations from a programmer to a compiler, to a language runtime system, or to hardware. The challenge for the system implementers is to build an efficient transactional memory infrastructure. This book presents an overview of the state of the art in the design and implementation of transactional memory systems, as of early spring 2010. Table of Contents: Introduction / Basic Transactions / Building on Basic Transactions / Software Transactional Memory / Hardware-Supported Transactional Memory / Conclusions

Transactional Memory, 2nd Edition

Chip multiprocessors - also called multi-core microprocessors or CMPs for short - are now the only way to build high-performance microprocessors, for a variety of reasons. Large uniprocessors are no longer scaling in performance, because it is only possible to extract a limited amount of parallelism from a typical instruction stream using conventional superscalar instruction issue techniques. In addition, one cannot simply ratchet up the clock speed on today's processors, or the power dissipation will become prohibitive in all but water-cooled systems. Compounding these problems is the simple fact that with the immense numbers of transistors available on today's microprocessor chips, it is too costly to design and debug ever-larger processors every year or two. CMPs avoid these problems by filling up a processor die with multiple, relatively simpler processor cores instead of just one huge core. The exact size of a CMPs cores can vary from very simple pipelines to moderately complex superscalar processors, but once a core has been selected the CMPs performance can easily scale across silicon process generations simply by stamping down more copies of the hard-to-design, high-speed processor core in each successive chip generation. In addition, parallel code execution, obtained by spreading multiple threads of execution across the various cores, can achieve significantly higher performance than would be possible using only a single core. While parallel threads are already common in many useful workloads, there are still important workloads that are hard to divide into parallel threads. The low inter-processor communication latency between the cores in a CMP helps make a much wider range of applications viable candidates for parallel execution than was possible with conventional, multi-chip multiprocessors; nevertheless, limited parallelism in key applications is the main factor limiting acceptance of CMPs in some types of systems.

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Chip Multiprocessor Architecture: Techniques to Improve Throughput and Latency

In this paper we propose a blocking-aware partitioning algorithm which allocates a task set on a multiprocessor (multi-core) platform in a way that the overall amount of blocking times of tasks are decreased. The algorithm reduces the total utilization which, in turn, has the potential to decrease the total number of required processors (cores). In this paper we evaluate our algorithm and compare it with an existing similar algorithm. The comparison criteria includes both number of schedulable systems as well as processor reduction performance.

Partitioning real-time systems on multiprocessors with shared resources

We consider the problem of balancing load items (tokens) on networks. Starting with an arbitrary load distribution, we allow in each round nodes to exchange tokens with their neighbors. The goal is to achieve a distribution where all nodes have nearly the same number of tokens. For the continuous case where tokens are arbitrarily divisible, most load balancing schemes correspond to Markov chains whose convergence is fairly well-understood in terms of their spectral gap. However, in many applications load items cannot be divided arbitrarily and we need to deal with the discrete case where the load is composed of indivisible tokens. This discretization entails a non-linear behavior due to its rounding errors, which makes the analysis much harder than in the continuous case. Therefore, it has been a major open problem to understand the limitations of discrete load balancing and its relation to the continuous case. We investigate several randomized protocols for different communication models in the discrete case. Our results demonstrate that there is almost no difference between the discrete and continuous case. For instance, for any regular network in the matching model, all nodes have the same load up to an additive constant in (asymptotically) the same number of rounds required in the continuous case. This generalizes and tightens the previous best result, which only holds for expander graphs.

Tight Bounds for Randomized Load Balancing on Arbitrary Network Topologies

This paper presents a review of the research status for real-time simulation of electric machines. The machine models considered are the lumped parameter models, including the phase-domain, $d$ – $q$ , and voltage-behind-reactance models, as well as the physics-based models, including the finite-element method and magnetic equivalent circuit models. These models are initially presented along with their relative advantages and disadvantages with respect to modeling fidelity and their computational intensity. A field-programmable gate array, a graphics processing unit, a chip multiprocessor, and computer clusters are the main hardware platforms for real-time simulations. An overview of such hardware platforms is presented and their comparative performances are evaluated with respect to real-time simulation of electric machines and drives on the basis of simulation acceleration, machine types, and modeling methodology.

Review of Hardware Platforms for Real-Time Simulation of Electric Machines

After a discussion of the task allocation problem in multi-core processor based parallel system, this paper gives the task allocation model, and proposes an iteration-based heuristic algorithm, which is composed of two rounds of operations, in which the processes are assigned to processing nodes in the first round and threads in process are assigned to processor cores in the second round respectively. Each round of operation partitions the task interaction graph by iterations with backtracking. Evaluation result shows that the algorithm can find near-optimal solutions in reasonable time, and behaves better than genetic algorithm when the number of threads increases, since it can find solutions in much less time than genetic algorithm.

Allocating Tasks in Multi-core Processor based Parallel System

I/O operation within transactions is one of the challenges for hardware transactional memory. This paper analyses the problem of I/O operations within transactions, and proposes a hardware transactional memory system architecture based on multi-core processor and current cache coherent mechanisms. The system supports execution of transactions by adding transactional buffer and related hardware and software. I/O operations within transactions are implemented by partial commit based on commit-lock, and blocking / waking-up of transactional threads. The solution solves or avoids the problems that I/O operations within transactions faced, including rollback, transaction migration and transactional buffer overflow. The system has been implemented by simulation. Its performance is evaluated by five benchmark applications. Simulation results show that the transactional programs executed in our system outperformed traditional lock-based programs.

Hardware Transactional Memory Supporting I/O Operations within Transactions

The invention discloses a method for blocking and awakening transaction threads in a hardware transactional memory system, which comprises the following steps of: arranging a transaction thread register in transaction supporting hardware and recording an identifier of a currently-executed transaction thread in the transaction thread register; when a blocked transaction thread is rescheduled and re-executed and if the blocked transaction thread is the same as the thread identifier in the register, continuing to submit the transaction; and if the blocked transaction thread is different from the thread identifier in the register, clearing a current transaction field and re-executing the transaction The method of the invention has the advantages of eliminating the limitation that the transactions in the hardware transactional memory system are necessarily executed in a time slice, solving the problem that a transaction cache is difficult to migrate and optimizing the high-efficiency execution of the transactions in the hardware transactional memory system

Method for blocking and awakening transaction threads in hardware transactional memory system

Efficient transaction nesting is one of the ongoing challenges for hardware transactional memory To increase efficiency of closed nesting, this paper proposes a conditional partial rollback (CPR) scheme which supports conditional partial rollback without increasing hardware complexities significantly In stead of rolling back to the outermost transaction as in commonly-used flattening model, the CPR scheme just rolls back to the conflicted transaction itself or one of its outer-level transactions if given conditions are satisfied By recording access status of each nested transaction, the scheme uses one global data set for all of the nested transactions rather than independent data set for each nested transaction Hardware transactional memory architecture with the support of CPR scheme is also proposed based on multi-core processor and current cache coherence mechanism The system is implemented by simulation, and evaluated using seven benchmark applications Evaluation results show that the CPR scheme achieves better performance and scalability than the flattening model which is commonly-used in hardware transactional memory

Efficient transaction nesting in hardware transactional memory

The invention discloses a time sequence controlling method for parallel simulation of a cluster system. The time sequence controlling method comprises the following steps of: establishing a logical clock for all processes of a target system according to a simulation event captured by a host system; and then maintaining and updating the state of the logical clock according to the running state of a simulation time in the target system to acquire the running time of the processes in the target system. Time-simulation events EVE are scanned according to host-target mapping relationship MAP to acquire an event buffer queue Qi of each target node in the target system. The method effectively improves the efficiency of a simulator on the premise of ensuring certain simulation accuracy for large-scale parallel system simulation.

He Li

Papers

Allocating Tasks in Multi-core Processor based Parallel System

Hardware Transactional Memory Supporting I/O Operations within Transactions

Method for blocking and awakening transaction threads in hardware transactional memory system

Efficient transaction nesting in hardware transactional memory

Time sequence controlling method for parallel simulation of cluster system