In this paper, a UART design is proposed. The design has an auto-tuning baud rate generator. For achieving the speed matching of the processor and UART interface, it takes asynchronous FIFOs as buffers to realize data exchange between UART and external devices. The whole design is functionally verified using ModelSim SE 6.0, and synthesized and optimized by Synplicity's Synplify Premier 9.6.2.

A universal asynchronous receiver transmitter design

Universal Asynchronous Receiver Transmitter) is used for serial communication. It is used for long distance and low cost process for transfer of data between pc and its devices. In general a UART operated with specific baud rate. To meet the complex communication demands it is not sufficient. To overcome this difficulty a multi channel UART is proposed in this paper. And the whole design is simulated with modelsim and synthesized with Xilinx software KeywordsBaud rate generator, First in First Out, Simulation.

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Design and Simulation of Multi Channel UART for Serial Communication

This paper presents the design and implementation method of a Universal Asynchronous Receiver Transmitter (UART) as a widely used serial communication protocol using Verilog Hardware Descriptional Language (HDL). In order to achieve the needs of latest complex communication system demands, a UART controller has been designed using FIFO (First In First Out) buffer technique for asynchronous serial data transmission between systems. Also, this reduces the delay, synchronisation error between sub-systems and provides a reliable, high performance logic solution for complex systems. The simulation and synthesis has been carried out using Modelsim DE 6.5 (inc. Mentor Graphics).

Design and Implementation of UART using FIFO for Serial Communication

Based on the FSM theory,the design of an embedded UART is performed in this paper,which supports the interface of an AMBA(Advanced Microcontroller Bus Architecture) 2.0 APB(Advanced Peripheral Bus).An improved asynchronous FIFO is proposed,which can generate empty and full flags more correctly while improving the transmission speed.Also,a new approach with easy operation and convenient realization is presented to deal with the fractional frequency division.It had been tested on FPGA.Embedded in the system,it had realized the transmission of data with that of ARM PSK system at any bit rate within 230 K in the condition of UART clock 12.5 M.Results of the test prove the feasibility of the design.

He Wei

Papers

Design of a High Performance Embedded UART