Open AccessJournal Article
Design of a High Performance Embedded UART
TLDR
An improved asynchronous FIFO is proposed, which can generate empty and full flags more correctly while improving the transmission speed and a new approach with easy operation and convenient realization is presented to deal with the fractional frequency division.Abstract:
Based on the FSM theory,the design of an embedded UART is performed in this paper,which supports the interface of an AMBA(Advanced Microcontroller Bus Architecture) 2.0 APB(Advanced Peripheral Bus).An improved asynchronous FIFO is proposed,which can generate empty and full flags more correctly while improving the transmission speed.Also,a new approach with easy operation and convenient realization is presented to deal with the fractional frequency division.It had been tested on FPGA.Embedded in the system,it had realized the transmission of data with that of ARM PSK system at any bit rate within 230 K in the condition of UART clock 12.5 M.Results of the test prove the feasibility of the design.read more
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Proceedings ArticleDOI
A universal asynchronous receiver transmitter design
TL;DR: The design has an auto-tuning baud rate generator for achieving the speed matching of the processor and UART interface and takes asynchronous FIFOs as buffers to realize data exchange between UART and external devices.
Journal ArticleDOI
Design and Simulation of Multi Channel UART for Serial Communication
N. B. S. Naveen,G. Rama Krishna +1 more
TL;DR: A multi channel UART is proposed in this paper for serial communication and the whole design is simulated with modelsim and synthesized with Xilinx software.
Design and Implementation of UART using FIFO for Serial Communication
TL;DR: In order to achieve the needs of latest complex communication system demands, a UART controller has been designed using FIFO (First In First Out) buffer technique for asynchronous serial data transmission between systems.