Showing papers by "Heinrich Meyr published in 1990"

High-rate Viterbi processor: a systolic array solution

Abstract: The main part of the Viterbi algorithm (VA) is a nonlinear feedback loop, the ACS recursion (add-compare-select recursion), which presents a bottleneck for high-speed implementations and cannot be circumvented by standard means. Because the two operations of the loop form an algebraic structure called semiring, it is shown that the ACS recursion of the Viterbi algorithm can therefore be written as a linear vector recursion. This allows the authors to employ the powerful techniques of parallel processing and pipelining, known for conventional linear systems, to achieve high throughput rates. Since the VA can be written as a linear vector recursion, it can be implemented by systolic arrays. For the class of shuffle exchange codes to be decoded by the Viterbi algorithm hardware-efficient code-optimized arrays are presented. It is shown that carry-save arithmetic can be used for the operations of ACS recursion, allowing each word-level operation to be pipelined and carried out by an efficient bit-level systolic array. >

Phase-, frequency-locked loops, and amplitude control

Abstract: Phase-Locked Loop Fundamentals. Phase-Locked Loop Tracking Performance in the Presence of Noise. Unaided Acquisition. Aided Acquisition. Loop Threshold. Amplitude Control. Automatic Frequency Control. Brief Review of Some Mathematical Fundamentals. Relaxation Times, Meantime Between Cycle Slips, Transition Rates, and Eigenvalues of Fokker-Planck Operators. Renewal Process Approach. The Matrix Eigenvalue Approach. Epilogue: Unexplored Topics. Index.

A 100 Mbit/s Viterbi decoder chip: novel architecture and its realization

Abstract: Installing new high-speed digital microwave and satellite communication links often leads to the need for fast Viterbi decoders (VDs). However, the main unit of a VD contains a nonlinear data-dependent feedback loop that limits the maximum achievable throughput rate. A conventional realization of this loop leads to the problem that good decoder performance requires a large wordlength, whereas a high data rate requires a small wordlength. The authors present an architecture which eliminates this trade-off by bit-level parallel processing. The architecture was used in the design of a fabricated 115 Mb/s VD chip for an 8-PSK (phase-shift keying) trellis code. This represents the fastest single-chip VD built to date. The less complex design ( >

Minimized method Viterbi decoding: 600 Mbit/s per chip

Abstract: The Viterbi algorithm is a common application of dynamic programming in communications. Since it has a nonlinear feedback loop, this loop is the bottleneck in high-data-rate implementations. It is shown that asymptotically the loop no longer has to be processed recursively, i.e. there is no feedback (resulting in negligible performance loss). This can be exploited to derive a purely feedforward method for Viterbi decoding, called the minimized method. It is demonstrated that the minimized method can be implemented very efficiently by a systolic architecture. This is shown on a chip design which achieves 600-Mb/s decoding speed per chip, for a K=3 convolutional code. By designing one cascadable module (chip), any speed up can be achieved simply by linearly adding modules to the implementation. >

Cascaded feedforward architectures for parallel Viterbi decoding

Abstract: The Viterbi algorithm (VA) is a common application of dynamic programming. Since it contains a nonlinear ACS (add-compare-select) feedback loop, this loop is the bottleneck in high-data-rate implementations. It is shown that, asymptotically, the ACS feedback no longer has to be processed recursively, i.e. there is no feedback, resulting in negligible performance loss. This can be exploited to derive purely feedforward architectures for Viterbi decoding, so that a modular cascadable implementation results. By designing one cascadable module, any speedup can be achieved simply by adding modules to the implementation. It is shown that optimization criteria, e.g. minimum latency or maximum hardware efficiency, are met by very different architectures. >

VLSI implementation of synchronization algorithms in a 100 Mbit/s digital receiver

Abstract: Digital VLSI implementation of the timing and carrier synchronization of digital receivers at very high data rates is addressed. The implementation of the synchronization algorithms for 100 Mb/s digital receiver for coded 8-PSK modulation is described. The digital receiver operates on a signal which is down-converted to baseband with a fixed-frequency oscillator and which is sampled at a fixed rate (no VCOs). The timing is recovered by estimating the timing offset and shifting the received samples by means of a digital interpolation. The carrier synchronization is carried out after matched filtering by estimating the carrier phase offset and rotating the samples accordingly. >

On the interaction between DSP-algorithms and VLSI-architecture

Abstract: The interaction between DSP (digital signal processing) algorithms and VLSI architecture is addressed, and it is shown at which levels architecture analysis has to be undertaken and at which levels new possibilities can be exploited. It is noted that the new possibilities of implementing algorithms and even complex systems on dedicated chips lead to the necessity of undertaking a careful analysis of architectures, not only at the algorithmic and the word level but, with increasing complexity of the chip, also down to the bit level. This allows a maximum of regularity to be extracted for the design of basic building blocks which are then used to construct the chip, so that the stated design conditions are optimally met. >