Showing papers by "Heinrich Meyr published in 1999"

Optimum receiver design for wireless broad-band systems using OFDM. I

Abstract: Orthogonal frequency-division multiplexing (OFDM) is the technique of choice in digital broad-band applications that must cope with highly dispersive transmission media at low receiver implementation cost. In this paper, we focus on the inner OFDM receiver and its functions necessary to demodulate the received signal and deliver soft information to the outer receiver for decoding. The effects of relevant nonideal transmission conditions are thoroughly analyzed: imperfect channel estimation, symbol frame offset, carrier and sampling clock frequency offset, time-selective fading, and critical analog components. Through an appropriate optimization criterion (signal-to-noise ratio loss), minimum requirements on each receiver synchronization function are systematically derived. An equivalent signal model encompassing the effects of all relevant imperfections is then formulated in a generalized framework. The paper concludes with an outline of synchronization strategies.

LISA—machine description language for cycle-accurate models of programmable DSP architectures

Abstract: This paper presents the machine description language LISA for the generation of bit- and cycle-accurate models of DSP processors. Based on a behavioral operation description, the architectural details and pipeline operations of modern DSP processors can be covered. Beyond the behavioral model, LISA descriptions include other architecture-related information like the instruction set. The information provided by LISA models enables automatic generation of simulators and assemblers which are essential elements of DSP software development environments. In order to proof the applicability of our approach, a realized model of the Texas Instruments TMS320C6201 DSP is presented and derived LISA code examples are given.

Low complexity space-frequency MLSE for multi-user COFDM

Abstract: The possibility of multi-user detection with receiver diversity has gotten a lot of attention lately. In this paper we show how this technique can be realized using OFDM together with bit interleaved coded modulation (BICM) as coding scheme. We present an optimum MLSE based metric for the decoding in such systems. Since the optimum metric proves to be rather complex we develop an alternative approach based on the ML estimation of the transmission symbols. Following this approach, with very little additional receiver-complexity, a true multi-user detection of bandwidth efficient QAM schemes in extremely selective environments becomes possible.

Optimized system synthesis of complex RT level building blocks from multirate dataflow graphs

Abstract: In order to cope with the ever increasing complexity of todays application specific integrated circuits, a building block based design methodology is established. The system is composed of high level building blocks of which some are reused from previous designs while others might have been created by behavioral synthesis. In data flow oriented designs, these blocks usually have complex non-matching interface properties, making it necessary to generate additional interfacing and controlling hardware to integrate them into an operable system.In this paper, an RTL-HDL code generation from a synchronous data flow representations is introduced, that efficiently automates the generation of the required additional hardware. While existing code generation approaches provide strong limitations concerning the building block interfacing properties, our method enables the integration of components that access their ports periodically with arbitrary patterns. In order to reduce interface register cost, a minimum-area retiming approach is taken to determine optimum building block activation times, which is known to have polynomial time complexity. The code generation methodology is compared to an existing approach using a simple case study.

Performance bounds for a UMTS RAKE receiver with imperfect timing synchronisation

Abstract: Performance bounds for a UMTS RAKE receiver with imperfect timing synchronisation are presented. Firstly, an analytical expression for the bit error probability (P/sub e/) performance of the RAKE receiver is derived. This analysis establishes that the bit error probability performance of the RAKE receiver is less sensitive to timing errors for higher spreading factors. However, significant performance degradations for all spreading factors confirm the need for timing synchronisation in the RAKE receiver. An extension of the analysis is presented for a multipath environment, allowing the derivation of an upper and a lower performance bound. The results indicate that a very simple interpolator providing 4 samples within a chip period results in a performance loss smaller than 0.15 dB.

Linear MMSE channel estimation for GSM

Abstract: A new channel estimation algorithm capable of exploiting a-priori knowledge about modulation and receive filters and the power delay profile of the physical channel is presented. In order to incorporate the a-priori knowledge into the linear minimum mean square error (LMMSE) channel estimator, a Bayesian approach is applied to an appropriate GSM system model. The performance of the new algorithm is compared to a conventional least squares (LS) channel estimator by means of analysis and simulations. Simulations are carried out for the standard GSM channel profiles (TU50, HT100, RA250). Information about the shape of the power delay profile is assumed to be unavailable to the receiver. The merit of the new channel estimator is confirmed by yielding an MSE approximately 1-2 dB lower than the LS estimator. The lower MSE translates into a BER advantage of approximately 0.25 dB. Exploiting additional knowledge about the shape of the power delay profile results in further BER performance improvements of up to 0.3 dB.

A universal coprocessor and its application for an ADSL modem

Abstract: Hardware implementations of digital signal processing tasks are typically considered inflexible and difficult to reuse. The current case study focuses on the design of a universal reusable coprocessor with application specific configurations to accelerate computational intensive tasks. The design methodology and the architecture is described for essential parts of an ADSL transceiver.

Exploring the UMTS WCDMA-receiver design space using a semianalytical approach

Abstract: A fast simulation technique for the analysis of the system performance of digital receivers is presented and applied to the UMTS terrestrial radio access (UTRA). This semianalytical method comprises the computation of receiver output statistics, conditioned on a static channel model, a given spreading sequence and a given transmitted symbol sequence. Averaging over the known channel tap probability density function and over all symbol sequences yields the system performance, conditioned on the selected spreading sequence. This method permits the qualitative classification and comparison of different detection algorithms for WCDMA in the performance-complexity design space. In the UTRA environment, the performance is shown to vary significantly with the choice of the OVSF spreading sequence. Simulation results for a RAKE receiver in indoor and outdoor scenarios are compared to lower and upper bounds of the probability of error of a maximum likelihood sequence estimation (MLSE) algorithm. It is shown that a RAKE receiver provides sufficient detection performance in medium-rate outdoor scenarios, whereas in high-rate indoor scenarios, especially in the uplink, alternative receiver structures must be considered.

Receive-filtering for GSM receivers in interference limited environments

Abstract: This paper addresses performance analysis and optimization of receive filters in a GSM system using an MLSE detection algorithm. In order to include the effects of adjacent and co-channel interference on the sequence estimation, appropriate signal models are derived. These models are used to calculate a performance measure for a system operating under these impairments. The resulting performance measure which depends on the interfering signals and the receiver filter characteristics is used to optimize the receive filter bandwidth with respect to minimum bit error probability.

Schnelle Simulation des TI-TMS320C54x DSP

Abstract: In diesem Beitrag wird eine neue Technik zur Simulation von DSPArchitekturen mit Pipeline vorgestellt. Im Gegensatz zu existierenden Simulatoren, die auf der interpretierenden Technik aufbauen, basiert unser Simulator auf dem Prinzip der kompilierten Simulation. Im Vergleich zu existierenden interpretierenden Prozessorsimulatoren sind Geschwindigkeitsteigerungen um zwei Größenordnungen bei gleichbleibender Genauigkeit der Simulation möglich. Als Folge dieser Geschwindigkeitssteigerung werden wesentlich kürzere Entwicklungszyklen bei der Entwicklung und Verifikation von DSP-Code möglich. Dieser Beitrag beschreibt die Technik der kompilierten Simulation anhand des TMS320C54x Prozessors von Texas Instruments. Die untersuchten Beispiele zeigen eine Geschwindigkeitssteigerung von 33 bis 155 im Vergleich zum Simulator sim54x von