Showing papers by "Heinrich Meyr published in 2001"
TL;DR: To show the impact of the synchronization algorithms-which are most critical in OFDM-on system performance and complexity, this paper considers the design of a complete receiver consisting of symbol synchronization, carrier/sampling clock synchronization and channel estimation.
Abstract: This paper details on the design of OFDM receivers. Special attention is paid to the OFDM-specific receiver functions necessary to demodulate the received signal and deliver soft information to the outer receiver for decoding. In part I of the paper, the effects of nonideal transmission conditions have been thoroughly analyzed. To show the impact of the synchronization algorithms-which are most critical in OFDM-on system performance and complexity we consider the design of a complete receiver consisting of symbol synchronization, carrier/sampling clock synchronization and channel estimation. The performance of the algorithms is analyzed and a qualitative estimate of the resulting complexity is given. This allows one to draw conclusions concerning the achievable system performance under realistic complexity assumptions.
485 citations
TL;DR: A retargetable framework for ASIP design which is based on machine descriptions in the LISA language is presented which can be generated automatically including high-level language C compiler, assembler, linker, simulator, and debugger frontend.
Abstract: The development of application-specific instruction-set processors (ASIP) is currently the exclusive domain of the semiconductor houses and core vendors. This is due to the fact that building such an architecture is a difficult task that requires expertise in different domains: application software development tools, processor hardware implementation, and system integration and verification. This paper presents a retargetable framework for ASIP design which is based on machine descriptions in the LISA language. From that, software development tools can be generated automatically including high-level language C compiler, assembler, linker, simulator, and debugger frontend. Moreover, for architecture implementation, synthesizable hardware description language code can be derived, which can then be processed by standard synthesis tools. Implementation results for a low-power ASIP for digital video broadcasting terrestrial acquisition and tracking algorithms designed with the presented methodology are given. To show the quality of the generated software development tools, they are compared in speed and functionality with commercially available tools of state-of-the-art digital signal processor and /spl mu/C architectures.
181 citations
TL;DR: It is shown that linear minimum mean square error channel estimation directly follows from the derivation and links average mutual information to the channel dynamics.
Abstract: The achievable rate of a coherent coded modulation digital communication system with data-aided channel estimation and a discrete equiprobable symbol alphabet is derived under the assumption that the system operates on a flat fading multiple-input/multiple-output channel and uses a perfect interleaver to combat the bursty nature of the channel. It is shown that linear minimum mean square error channel estimation directly follows from the derivation and links average mutual information to the channel dynamics. Based on the assumption that known training symbols are transmitted, the achievable rate of the system is optimized with respect to the amount of training information needed.
159 citations
04 Nov 2001
TL;DR: A retargetable framework for ASIP design which is based on machine descriptions in the LISA language is presented which can be automatically generated including HLL C-compiler, assembler, linker, simulator and debugger frontend and synthesizable HDL code can be derived.
Abstract: The development of application specific instruction set processors (ASIP) is currently the exclusive domain of the semiconductor houses and core vendors. This is due to the fact that building such an architecture is a difficult task that requires expertise knowledge in different domains: application software development tools, processor hardware implementation, and system integration and verification. This paper presents a retargetable framework for ASIP design which is based on machine descriptions in the LISA language. From that, software development tools can be automatically generated including HLL C-compiler, assembler, linker, simulator and debugger frontend. Moreover, synthesizable HDL code can be derived which can then be processed by standard synthesis tools. Implementation results for a low-power ASIP for DVB-T acquisition and tracking algorithms designed with the presented methodology will be given.
97 citations
TL;DR: The constrained capacity of a coherent coded modulation digital communication system with data-aided channel estimation and a discrete, equiprobable symbol alphabet and the achievable rate of the system is optimized with respect to the amount of training information needed.
Abstract: The constrained capacity of a coherent coded modulation (CM) digital communication system with data-aided channel estimation and a discrete, equiprobable symbol alphabet is derived under the assumption that the system operates on a flat fading channel and uses an interleaver to combat the bursty nature of the channel. It is shown that linear minimum mean square error channel estimation directly follows from the derivation and links average mutual information to the channel dynamics. Based on the assumption that known training symbols are transmitted, the achievable rate of the system is optimized with respect to the amount of training information needed. Furthermore, the results are compared to the additive white Gaussian noise channel, and the case when ideal channel state information is available at the receiver.
88 citations
TL;DR: Several new estimation algorithms are developed that are tailored to channels with closely spaced multipaths that leads to performance improvements in terms of signal-to-noise ratio (SNR) at moderate bit error rates, and even manages to track the channel in conditions where conventional tracking algorithms fail completely.
Abstract: This paper deals with the problem of channel tracking for RAKE receivers in propagation environments characterized by closely spaced multipath components. After outlining why conventional single-path channel tracking algorithms fail in such scenarios, several new estimation algorithms are developed that are tailored to channels with closely spaced multipaths. This is achieved by removing or minimizing self-interference caused by multipath components. Other interfering users are treated as noise. Both timing tracking and phasor tracking and their interaction are covered in this paper. The derived algorithms are benchmarked against perfect channel knowledge on one hand and conventional tracking algorithms on the other hand, both in a UMTS test scenario. In moderate scenarios, the use of these new algorithms leads to performance improvements of up to 2 dB, in terms of signal-to-noise ratio (SNR) at moderate bit error rates, and even manages to track the channel in conditions where conventional tracking algorithms fail completely.
72 citations
09 Oct 2001
TL;DR: In this paper, the authors provide a complete treatment on the theoretical and practical aspects of synchronization and channel estimation from the standpoint of digital signal processing, focusing on the systematic approach to algorithm development, and the linked algorithm-architecture methodology in digital receiver design.
Abstract: From the Publisher:
Digital Communication Receivers offers a complete treatment on the theoretical and practical aspects of synchronization and channel estimation from the standpoint of digital signal processing. The focus on these increasingly important topics, the systematic approach to algorithm development, and the linked algorithm-architecture methodology in digital receiver design are unique features of this book. The material is structured according to different classes of transmission channels. In Part C, baseband transmission over wire or optical fiber is addressed. Part D covers passband transmission over satellite or terrestrial wireless channels. Part E deals with transmission over fading channels. Designed for the practicing communication engineer and the graduate student, the book places considerable emphasis on helpful examples, summaries, illustrations, and bibliographies. Contents include basic material, baseband communications, passband transmission, receiver structure for PAM signals, synthesis of synchronization algorithms, performance analysis of synchronizers, bit error degradation caused by random tracking errors, frequency estimation, timing adjustment by interpolation, DSP system implementation, characterization, modeling, and simulation of linear fading channels, detection and parameter synchronization on fading channels, receiver structures for fading channels, parameter synchronization for flat fading channels, and parameter synchronization for selective fading channels.
68 citations
13 Mar 2001
TL;DR: A new hardware-software co-simulation framework enabling fast prototyping in system-on-chip designs and a hardware modeling strategy using abstract macro-cycle based C++ processes to increase hardware modeling efficiency and simulation speed is presented.
Abstract: We present a new hardware-software co-simulation framework enabling fast prototyping in system-on-chip designs. On the software side, the machine description language LISA allows the generation of bit-true models of programmable architectures on various levels-from instruction-set to phase accuracy. Based on these models, a complete tool-suite consisting of fast compiled processor simulator assembler, linker HLL-compiler as well as co-simulation interface can be generated automatically. On the hardware side, the SystemC simulation class library is employed and enhanced with our generic co-simulation interface that enables the coupling of hardware and software models specified at various levels of abstraction. Besides that, a hardware modeling strategy using abstract macro-cycle based C++ processes to increase hardware modeling efficiency and simulation speed is presented.
57 citations
25 Nov 2001
TL;DR: An adaptive scheme based on the well known least mean-squares (LMS) approach is presented, and the estimation algorithm converges to its optimum independently of the phase noise characteristic of a specific oscillator, or slowly varying temperatures.
Abstract: Wideband communication systems operating at high SNR's, like many point to point communication systems, generally suffer from poor oscillator phase noise characteristics. When QPSK pilot symbols are inserted periodically into a QAM data symbol stream, it is possible to obtain phase noise estimates for these time instants. Wiener interpolation is used to generate linear minimum mean-squared error (LMMSE) estimates for the time instants between those values. Finally, an adaptive scheme based on the well known least mean-squares (LMS) approach is presented. Using this adaptive method, the estimation algorithm converges to its optimum independently of the phase noise characteristic of a specific oscillator, or slowly varying temperatures.
42 citations
30 Sep 2001
TL;DR: In this article, the authors discuss the application of static scheduling techniques to retargetable simulation tools based on the processor description language LISA, and results are presented for two selected processor architectures.
Abstract: Instruction set simulators are indispensable tools for both the design of programmable architectures and software development. However, due to a constantly increasing processor complexity and the frequent demand for cycle-accurate models, such simulators have become defectively slow. The principle of compiled simulation addresses this shortcoming. Compiled simulators make use of a priori knowlegde to accelerate simulation, with the highest efficiency achieved by employing static scheduling techniques.In the past, such statically scheduled simulators have only been implemented for specific DSP architectures. The approach presented here discusses the application of static scheduling techniques to retargetable simulation tools based on the processor description language LISA. Principles and implementation issues are discussed in this paper, and results are presented for two selected processor architectures.
32 citations
22 Jun 2001
TL;DR: This novel approach additionally permits a code transformation to integral data types for fast simulation of the bit-true behavior and a speedup by a factor of 20 to 400 can be achieved compared to library based simulation.
Abstract: This paper presents a design environment which enables fast simulation of fixed-point signal processing algorithms. In contrast to existing approaches which use C/C++ libraries for the emulation of generic fixed-point data types, this novel approach additionally permits a code transformation to integral data types for fast simulation of the bit-true behavior. A speedup by a factor of 20 to 400 can be achieved compared to library based simulation.
13 Mar 2001
TL;DR: This paper presents a methodology to automatically generate production quality software development tools for programmable architectures using the machine description language LISA and the feasibility of automatically generating simulator, assembler, linker and graphical debugger frontend are discussed.
Abstract: This paper presents a methodology to automatically generate production quality software development tools for programmable architectures using the machine description language LISA. Various architectures presenting diverse architectural originalities will be presented and the feasibility of automatically generating simulator, assembler, linker and graphical debugger frontend are discussed. The presented approach is not limited to a fixed abstraction level-case studies of the Texas Instruments C62x and C54x, the Analog Devices ADSP2101 as well as the ARM7 show the applicability of the methodology from cycle/phase to instruction accurate models.
07 May 2001
TL;DR: This paper presents a methodology which enables the generation of C62/spl times/ optimized fixed-point C-code from a floating-point description of an algorithm using the code transformation techniques illustrated in this paper.
Abstract: This paper presents a methodology which enables the generation of C62/spl times/ optimized fixed-point C-code from a floating-point description of an algorithm. The FRIDGE design environment transforms floating-point ANSI-C code with local fixed-point annotations into an internal bit-true representation. From this representation we generate C62/spl times/ optimized integer C code utilizing the code transformation techniques illustrated in this paper. A benchmark is presented comparing the efficiency of the generated code with C67/spl times/ C-code, C62/spl times/ floating-point emulation and generic integer ANSI-C code.
26 Sep 2001
TL;DR: This case study focuses on an ASIP design methodology considering the classical parameters computational performance and area as well as energy consumption simultaneously, and reveals a potential of about one order of magnitude in energy savings for these optimizations.
Abstract: Application specific instruction set processors (ASIPs) are an excellent architecture for mixed control/data-flow oriented tasks with medium to low data rate and high complexity. The main advantage of ASIPs is the higher flexibility due to programmability compared to dedicated hardware. A drawback of this design style is an increase in power consumption. The current case study focuses on an ASIP design methodology considering the classical parameters computational performance and area as well as energy consumption simultaneously. Several ASIP power optimization options have been applied and evaluated: clock-gating, logic netlist restructuring, ISA optimization, instruction memory power reduction, and use of a dedicated coprocessor. These optimizations are demonstrated with the WORE (ISS-core) ASIP for DVB-T acquisition and tracking algorithms. The results reveal a potential of about one order of magnitude in energy savings for these optimizations.
07 May 2001
TL;DR: This paper presents a survey on modeling issues of programmable architectures using the machine description language LISA and the feasibility of automatically generating simulator, assembler, linker and graphical debugger frontend discussed.
Abstract: This paper presents a survey on modeling issues of programmable architectures using the machine description language LISA. Various architectures presenting diverse architectural characteristics are presented and the feasibility of automatically generating simulator, assembler, linker and graphical debugger frontend discussed. The presented approach is not limited to a fixed abstraction level-case studies of the Texas Instruments C62/spl times/ and C54/spl times/, the Analog Devices ADSP2101 as well as the ARM7 show the applicability of the methodology from cycle/phase to instruction accurate models.
26 Sep 2001
TL;DR: This work proposes a system level design and refinement methodology based on the SystemC class library that is able to define successively a feasible system architecture coping with the processing and memory bandwidth requirements.
Abstract: We propose a system level design and refinement methodology based on the SystemC class library. We address design space exploration and performance profiling at the highest possible level of abstraction. System level design starts with the initial functional specification and validation of the system behavior in SystemC. The refinement methodology covers architecture exploration and results in an executable system architecture model, which is able to generate the relevant profiling data and to verify if the chosen architecture meets the performance requirements. We have applied this methodology to a 100 million gate design of a 3D graphic processor. We were able to demonstrate the feasibility and define the final system architecture within 2 months. This 3D processor implements the ray-tracing rendering paradigm on one chip allowing real time rendering of 3D scenes with photo-realistic quality. Based on the results of this case study, we present the benefits of our methodology to define successively a feasible system architecture coping with the processing and memory bandwidth requirements.
25 Nov 2001
TL;DR: This paper addresses the subject of signal generation in the transmit path of a digital communications system and introduces the technique of rate adaptation and modulation, which generates the transmit signal immediately at sample rate and thus saves the interpolator.
Abstract: This paper addresses the subject of signal generation in the transmit path of a digital communications system. In order to minimize cost it is desirable to use a free running oscillator instead of a controlled oscillator. The signal generation task can be separated into pulse shaping at a fixed symbol rate and rate conversion to the arbitrary sampling rate by means of interpolation and decimation. As an alternative, we introduce the technique of rate adaptation and modulation, which generates the transmit signal immediately at sample rate and thus saves the interpolator. We compare the complexity of the two approaches both applied to the uplink of a UNITS system, discuss their advantages and disadvantages, and show that the use of an expensive controlled oscillator can be avoided in favor of a free running oscillator.
26 Sep 2001
TL;DR: This hypothesis is based on the fundamental trade-off between computational efficiency (MOPS/mW) and flexibility: while programmable devices have the highest degree of flexibility, they have at least a two to three orders of magnitude smaller computational efficiency than the intrinsic computational efficiency of fixed architectures.
Abstract: Summary form only given. Advanced communication systems obey a generalized Moore's law. Not only does hardware complexity double every 18 months, but also the other performance indicators such as program size or memory content-increase by a factor of two in a period of one and a half and three years, to mention two examples. The drawing force behind this growth is the algorithmic complexity which is needed to design communication systems operating close to the information theoretic limits: near optimum system performance is bound to exponentially increasing algorithmic complexity. Stated differently, the usefulness for the user only grows logarithmically with complexity. Basically, this logarithmic complexity provides the rational for the continued growth of the semiconductor industry. Advanced communication systems will be implemented as reconfigurable, heterogeneous multiprocessor platforms. This hypothesis is based on the fundamental trade-off between computational efficiency (MOPS/mW) and flexibility. While programmable devices (processors or DSPs) have the highest degree of flexibility, they have at least a two to three orders of magnitude smaller computational efficiency than the intrinsic computational efficiency (ICE) of fixed architectures. Hence, since power is the limiting factor, the SOCs of the future will carefully match algorithm with architecture to achieve an optimum. ("just as much flexibility as needed"). These SOC's will, therefore, become application specific platforms.
16 Nov 2001
TL;DR: A technique for program analysis targeting digital signal processing systems utilized by the FRIDGE design environment to transform floating-point systems into fixed- point systems is presented.
Abstract: We present a technique for program analysis targeting digital signal processing systems. It is utilized by the FRIDGE design environment to transform floating-point systems into fixed-point systems. While the transforming algorithms have been subject to a number of other publications, we now put the focus on the novel technique of program analysis employed by FRIDGE. The code is analyzed by interpreting it without processing any concrete input data. This enables most accurate analysis even capable of detecting dynamic code properties without relying on input vectors as e. g. profilers do.
02 Sep 2001
TL;DR: It is shown that linear minimum mean square error (LMMSE) channel estimation directly follows from the derivation, and links average mutual information to the channel dynamics.
Abstract: The achievable rate of a coherent coded modulation (CM) digital communication system with data-aided channel estimation and a discrete, equiprobable symbol alphabet is derived under the assumption that the system operates on a flat fading MIMO channel and uses an interleaver to combat the bursty nature of the channel. It is shown that linear minimum mean square error (LMMSE) channel estimation directly follows from the derivation, and links average mutual information to the channel dynamics. Based on the assumption that known training symbols are transmitted, the achievable rate of the system is optimized with respect to the amount of training information needed.