Showing papers by "Heinrich Meyr published in 2002"

A universal technique for fast and flexible instruction-set architecture simulation

Abstract: In the last decade, instruction-set simulators have become an essential development tool for the design of new programmable architectures. Consequently, the simulator performance is a key factor for the overall design efficiency. Based on the extremely poor performance of commonly used interpretive simulators, research work on fast compiled instruction-set simulation was started ten years ago. However, due to the restrictiveness of the compiled technique, it has not been able to push through in commercial products. This paper presents a new retargetable simulation technique which combines the performance of traditional compiled simulators with the flexibility of interpretive simulation. This technique is not limited to any class of architectures or applications and can be utilized from architecture exploration up to end-user software development. The work-flow and the applicability of the so-called just-in-time cache compiled simulation (JIT-CCS) technique will be demonstrated by means of state of the art real world architectures.

Architecture Exploration for Embedded Processors with LISA

Abstract: Foreword. Preface. 1: Introduction. 1. Processor Categories. 2. Advent of ASIPs in System-on-Chip Design. 3. Organization of this Book. 2: Traditional Asip Design Methodology. 1. Related Work. 2. Motivation of this Work. 3: Processor Models For Asip Design. 1. LISA Language. 2. Model Requirements of Tools. 3. Abstraction Levels. 4. Concluding Remarks. 4: Lisa Processor Design Platform. 1. Hardware Designer Platform. 2. Software Designer Platform. 3. System Integrator Platform. 4. Concluding Remarks. 5: Architecture Exploration. 1. From Specification to Implementation. 2. Architecture Exploration Using LISA. 3. Concluding Remarks. 6: Architecture Implementation. 1. The ICORE Architecture. 2. Architecture Generation from LISA. 3. Case Study. 4. Concluding Remarks. 7: Software Tools For Application Design. 1. Code Generation Tools. 2. Simulation. 3. Debugging. 4. Case Studies. 5. Concluding Remarks. 8: System Integration And Verification. 1. Platform-Based Design. 2. Enabling Platform-Based Design. 3. Software Simulator Integration. 4. Case Study: CoCentric System Studio. 5. Concluding Remarks. 9: Summary And Outlook. 1. Processor Modeling. 2. Architecture Exploration. 3. Software Development Tools. 4. Architecture Implementation. 5. Concluding Remarks. Appendices: Abbreviations.Grammar of the LISA Language. Sample ARM7 LISA Model. The ICORE Architecture. List of Figures. List of Examples. List of Tables. Bibliography. About the Authors.

Architecture Implementation Using the Machine Description Language LISA

Abstract: The development of application specific instruction set processors comprises several design phases: architecture exploration, software tools design, system verification and design implementation. The LISA processor design platform (LPDP) based on machine descriptions in the LISA language provides one common environment for these design phases. Required software tools for architecture exploration and application development can be generated from one sole specification. This paper focuses on the implementation phase and the generation of synthesizable HDL code from a LISA model. The derivation of the architectural structure, decoder and even approaches for the implementation of the data path are presented. Moreover the synthesis results of a generated and a handwritten implementation of a low-power DVB-T post processing unit are compared.

Design and DSP implementation of fixed-point systems

Abstract: This article is an introduction to the FRIDGE design environment which supports the design and DSP implementation of fixed-point digital signal processing systems. We present the tool-supported transformation of signal processing algorithms coded in floating-point ANSI C to a fixed-point representation in SystemC. We introduce the novel approach to control and data flow analysis, which is necessary for the transformation. The design environment enables fast bit-true simulation by mapping the fixed-point algorithm to integral data types of the host machine. A speedup by a factor of 20 to 400 can be achieved compared to C++-library-based bit-true simulation. FRIDGE also provides a direct link to DSP implementation by processor specific C code generation and advanced code optimization.

Application specific compiler/architecture codesign: a case study

Abstract: This paper proposes an architecture exploration methodology for application specific instruction set processors (ASIPs) including a C compiler and a VHDL model in the exploration loop. For a given application the target architecture is an instance of the scalable ALICE VLIW architecture which will be presented in this paper. In a case study it will be explained how the LISA processor design platform in conjunction with the CoSy compiler environment significantly reduces the time for exploration cycles. Using a typical telecommunications application, the quality of the resulting architecture and its performance are compared to the ICORE2 processor - a manually designed ASIP for efficient processing of computation intensive kernels.

Low complexity high resolution subspace-based delay estimation for DS-CDMA

Abstract: We consider the problem of estimating the propagation delays of a synchronous direct-sequence code division multiple access (DS-CDMA) system operating over a multipath fading channel. In a mobile receiver, the task of delay estimation can be divided into an acquisition of all multipath delays and subsequent tracking of the individual delays e.g. with a RAKE structure. Both tasks are especially challenging in indoor scenarios which commonly exhibit low delay-spread and thus require a high resolution of the estimation algorithms. A novel delay acquisition algorithm is presented, which is able to resolve multipaths whose delay difference is below one chip duration with high probability of acquisition and low computational complexity. It is based on a decomposition of the time-averaged correlation matrix of the output of a sliding correlator into signal and noise subspaces, with subsequent MUSIC spectrum computation and maximum search. The performance of the algorithm is assessed by means of computer simulations.

Efficient Design Flow for Fixed-Point Systems

Abstract: The complexity of DSP systems grows at an ever-increasing rate while the implementation of these designs must meet criteria like minimum cost and a short time to market. Hence there is a growing need for efficient design automation and a seamless design flow that allows the execution of the design steps at the highest suitable level of abstraction.

System Integration and Verification

Abstract: Today, typical single chip electronic system implementations include a mixture of µCs, DSPs as well as shared memory, dedicated logic (ASICs), and interconnect components [182]. To enable designers to create such complex systems, new system design methodologies have been introduced in recent years. One example is the orthogonalization of concerns [140], i.e. the separation of various aspects of design to allow a more effective exploration of alternative solutions and to ease verification. Here, it is proposed to separate between: function (what the system is supposed to do) and architecture (how it does it), and communication and computation.